-- ------------------------------------------------------------------------- --
--                  This circuit was generated by CirGen                     --
-- ------------------------------------------------------------------------- --

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity CIRCUIT is
   port(

      -- Primary input gates
      PRI_IN_0 : in  std_logic_vector(15 downto 0);
      PRI_IN_1 : in  std_logic_vector(15 downto 0);
      PRI_IN_2 : in  std_logic_vector(15 downto 0);
      PRI_IN_3 : in  std_logic_vector(15 downto 0);
      PRI_IN_4 : in  std_logic_vector(15 downto 0);
      PRI_IN_5 : in  std_logic_vector(15 downto 0);
      PRI_IN_6 : in  std_logic_vector(15 downto 0);
      PRI_IN_7 : in  std_logic_vector(15 downto 0);
      PRI_IN_8 : in  std_logic_vector(15 downto 0);
      PRI_IN_9 : in  std_logic_vector(15 downto 0);

      -- Primary output gates
      PRI_OUT_0 : out std_logic_vector(15 downto 0);
      PRI_OUT_1 : out std_logic_vector(15 downto 0);
      PRI_OUT_2 : out std_logic_vector(15 downto 0);
      PRI_OUT_3 : out std_logic_vector(15 downto 0);
      PRI_OUT_4 : out std_logic_vector(15 downto 0);
      PRI_OUT_5 : out std_logic_vector(15 downto 0);
      PRI_OUT_6 : out std_logic_vector(15 downto 0);
      PRI_OUT_7 : out std_logic_vector(15 downto 0);
      PRI_OUT_8 : out std_logic_vector(15 downto 0);
      PRI_OUT_9 : out std_logic_vector(15 downto 0);

      -- Primary control gates
      C_MUX2_1_SEL : in  std_logic;
      C_MUX2_2_SEL : in  std_logic;
      C_MUX2_3_SEL : in  std_logic;
      C_MUX2_4_SEL : in  std_logic;
      C_MUX2_5_SEL : in  std_logic;
      C_MUX2_6_SEL : in  std_logic;
      C_MUX2_7_SEL : in  std_logic;
      C_MUX2_8_SEL : in  std_logic;
      C_MUX2_9_SEL : in  std_logic;
      C_MUX2_10_SEL : in  std_logic;
      C_MUX2_11_SEL : in  std_logic;
      C_MUX2_12_SEL : in  std_logic;
      C_MUX2_13_SEL : in  std_logic;
      C_MUX2_14_SEL : in  std_logic;
      C_MUX2_15_SEL : in  std_logic;
      C_MUX2_16_SEL : in  std_logic;
      C_MUX2_17_SEL : in  std_logic;
      C_MUX2_18_SEL : in  std_logic;
      C_MUX2_19_SEL : in  std_logic;
      C_MUX2_20_SEL : in  std_logic;
      C_MUX2_21_SEL : in  std_logic;
      C_MUX2_22_SEL : in  std_logic;
      C_MUX2_23_SEL : in  std_logic;
      C_MUX2_24_SEL : in  std_logic;
      C_MUX2_25_SEL : in  std_logic;
      CLK : in  std_logic
   );
end entity CIRCUIT;
-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture CIRCUIT_arch of CIRCUIT is

-- ############################# USED COMPONENTS ##############################

      component ADD
         generic (
            width_a : positive);  
         port(
            a : in std_logic_vector (width_a - 1 downto 0);
            b : in std_logic_vector (width_a - 1 downto 0);
            q : out std_logic_vector(width_a - 1 downto 0)
         );
      end component ADD;
    
      component MUX2
         generic (
            width_a : positive);  
         port(
            -- Inputs
            a   : in  std_logic_vector(width_a - 1 downto 0);
            b   : in  std_logic_vector(width_a - 1 downto 0);
            sel : in  std_logic;
            -- Outputs
            q   : out std_logic_vector(width_a - 1 downto 0)
         );
      end component MUX2;
    
      component REG
         generic (
            width_a : positive);  
         port(
            -- Inputs
            d   : in  std_logic_vector(width_a - 1 downto 0);
            clk : in  std_logic;
            -- Outputs
            q   : out std_logic_vector(width_a - 1 downto 0)
         );
      end component REG;
    
      component SUB
         generic (
            width_a : positive);  
         port(
            -- Inputs
            a : in std_logic_vector(width_a - 1 downto 0);
            b : in std_logic_vector(width_a - 1 downto 0);
            -- Outputs
            q : out std_logic_vector(width_a - 1 downto 0)
         );
      end component SUB;
    

-- #############################   CONNECTIONS   ##############################

   -- DATA CONNECTIONS
   signal mux2_5_q_c : std_logic_vector(15 downto 0);
   signal reg_10_q_c : std_logic_vector(15 downto 0);
   signal mux2_6_q_c : std_logic_vector(15 downto 0);
   signal mux2_17_q_c : std_logic_vector(15 downto 0);
   signal add_13_q_c : std_logic_vector(15 downto 0);
   signal reg_14_q_c : std_logic_vector(15 downto 0);
   signal add_25_q_c : std_logic_vector(15 downto 0);
   signal reg_16_q_c : std_logic_vector(15 downto 0);
   signal reg_17_q_c : std_logic_vector(15 downto 0);
   signal reg_18_q_c : std_logic_vector(15 downto 0);
   signal reg_20_q_c : std_logic_vector(15 downto 0);
   signal mux2_1_q_c : std_logic_vector(15 downto 0);
   signal reg_19_q_c : std_logic_vector(15 downto 0);
   signal reg_27_q_c : std_logic_vector(15 downto 0);
   signal reg_12_q_c : std_logic_vector(15 downto 0);
   signal reg_28_q_c : std_logic_vector(15 downto 0);
   signal reg_30_q_c : std_logic_vector(15 downto 0);
   signal sub_14_q_c : std_logic_vector(15 downto 0);
   signal mux2_15_q_c : std_logic_vector(15 downto 0);
   signal mux2_16_q_c : std_logic_vector(15 downto 0);
   signal reg_34_q_c : std_logic_vector(15 downto 0);
   signal reg_35_q_c : std_logic_vector(15 downto 0);
   signal mux2_4_q_c : std_logic_vector(15 downto 0);
   signal reg_36_q_c : std_logic_vector(15 downto 0);
   signal reg_37_q_c : std_logic_vector(15 downto 0);
   signal reg_38_q_c : std_logic_vector(15 downto 0);
   signal reg_26_q_c : std_logic_vector(15 downto 0);
   signal add_22_q_c : std_logic_vector(15 downto 0);
   signal mux2_22_q_c : std_logic_vector(15 downto 0);
   signal mux2_13_q_c : std_logic_vector(15 downto 0);
   signal reg_40_q_c : std_logic_vector(15 downto 0);
   signal mux2_12_q_c : std_logic_vector(15 downto 0);
   signal sub_12_q_c : std_logic_vector(15 downto 0);
   signal mux2_23_q_c : std_logic_vector(15 downto 0);
   signal mux2_8_q_c : std_logic_vector(15 downto 0);
   signal sub_16_q_c : std_logic_vector(15 downto 0);
   signal reg_7_q_c : std_logic_vector(15 downto 0);
   signal mux2_9_q_c : std_logic_vector(15 downto 0);
   signal mux2_11_q_c : std_logic_vector(15 downto 0);
   signal mux2_21_q_c : std_logic_vector(15 downto 0);
   signal reg_43_q_c : std_logic_vector(15 downto 0);
   signal reg_44_q_c : std_logic_vector(15 downto 0);
   signal reg_45_q_c : std_logic_vector(15 downto 0);
   signal reg_31_q_c : std_logic_vector(15 downto 0);
   signal mux2_3_q_c : std_logic_vector(15 downto 0);
   signal reg_46_q_c : std_logic_vector(15 downto 0);
   signal mux2_20_q_c : std_logic_vector(15 downto 0);
   signal reg_47_q_c : std_logic_vector(15 downto 0);
   signal reg_48_q_c : std_logic_vector(15 downto 0);
   signal reg_32_q_c : std_logic_vector(15 downto 0);
   signal mux2_7_q_c : std_logic_vector(15 downto 0);
   signal sub_25_q_c : std_logic_vector(15 downto 0);
   signal mux2_10_q_c : std_logic_vector(15 downto 0);
   signal add_2_q_c : std_logic_vector(15 downto 0);
   signal reg_22_q_c : std_logic_vector(15 downto 0);
   signal mux2_14_q_c : std_logic_vector(15 downto 0);
   signal reg_24_q_c : std_logic_vector(15 downto 0);
   signal reg_25_q_c : std_logic_vector(15 downto 0);
   signal mux2_24_q_c : std_logic_vector(15 downto 0);
   signal reg_29_q_c : std_logic_vector(15 downto 0);
   signal reg_1_q_c : std_logic_vector(15 downto 0);
   signal reg_11_q_c : std_logic_vector(15 downto 0);
   signal mux2_25_q_c : std_logic_vector(15 downto 0);
   signal reg_5_q_c : std_logic_vector(15 downto 0);
   signal reg_2_q_c : std_logic_vector(15 downto 0);
   signal reg_21_q_c : std_logic_vector(15 downto 0);
   signal mux2_19_q_c : std_logic_vector(15 downto 0);
   signal reg_3_q_c : std_logic_vector(15 downto 0);
   signal reg_8_q_c : std_logic_vector(15 downto 0);
   signal reg_23_q_c : std_logic_vector(15 downto 0);
   signal reg_4_q_c : std_logic_vector(15 downto 0);
   signal mux2_2_q_c : std_logic_vector(15 downto 0);
   signal reg_6_q_c : std_logic_vector(15 downto 0);
   signal mux2_18_q_c : std_logic_vector(15 downto 0);
   signal reg_9_q_c : std_logic_vector(15 downto 0);
   signal sub_24_q_c : std_logic_vector(15 downto 0);
   signal add_6_q_c : std_logic_vector(15 downto 0);
   signal add_7_q_c : std_logic_vector(15 downto 0);
   signal add_16_q_c : std_logic_vector(15 downto 0);
   signal add_20_q_c : std_logic_vector(15 downto 0);
   signal sub_20_q_c : std_logic_vector(15 downto 0);
   signal sub_4_q_c : std_logic_vector(15 downto 0);
   signal sub_6_q_c : std_logic_vector(15 downto 0);
   signal sub_1_q_c : std_logic_vector(15 downto 0);
   signal sub_8_q_c : std_logic_vector(15 downto 0);
   signal add_10_q_c : std_logic_vector(15 downto 0);
   signal sub_5_q_c : std_logic_vector(15 downto 0);
   signal reg_13_q_c : std_logic_vector(15 downto 0);
   signal add_21_q_c : std_logic_vector(15 downto 0);
   signal reg_15_q_c : std_logic_vector(15 downto 0);
   signal add_4_q_c : std_logic_vector(15 downto 0);
   signal sub_22_q_c : std_logic_vector(15 downto 0);
   signal add_5_q_c : std_logic_vector(15 downto 0);
   signal add_24_q_c : std_logic_vector(15 downto 0);
   signal sub_18_q_c : std_logic_vector(15 downto 0);
   signal sub_3_q_c : std_logic_vector(15 downto 0);
   signal sub_9_q_c : std_logic_vector(15 downto 0);
   signal sub_2_q_c : std_logic_vector(15 downto 0);
   signal sub_17_q_c : std_logic_vector(15 downto 0);
   signal sub_11_q_c : std_logic_vector(15 downto 0);
   signal sub_7_q_c : std_logic_vector(15 downto 0);
   signal sub_13_q_c : std_logic_vector(15 downto 0);
   signal add_19_q_c : std_logic_vector(15 downto 0);
   signal add_11_q_c : std_logic_vector(15 downto 0);
   signal add_17_q_c : std_logic_vector(15 downto 0);
   signal add_18_q_c : std_logic_vector(15 downto 0);
   signal sub_21_q_c : std_logic_vector(15 downto 0);
   signal reg_33_q_c : std_logic_vector(15 downto 0);
   signal add_14_q_c : std_logic_vector(15 downto 0);
   signal sub_19_q_c : std_logic_vector(15 downto 0);
   signal add_15_q_c : std_logic_vector(15 downto 0);
   signal sub_10_q_c : std_logic_vector(15 downto 0);
   signal add_3_q_c : std_logic_vector(15 downto 0);
   signal reg_39_q_c : std_logic_vector(15 downto 0);
   signal add_9_q_c : std_logic_vector(15 downto 0);
   signal reg_41_q_c : std_logic_vector(15 downto 0);
   signal reg_42_q_c : std_logic_vector(15 downto 0);
   signal sub_23_q_c : std_logic_vector(15 downto 0);
   signal add_1_q_c : std_logic_vector(15 downto 0);
   signal add_12_q_c : std_logic_vector(15 downto 0);
   signal sub_15_q_c : std_logic_vector(15 downto 0);
   signal add_23_q_c : std_logic_vector(15 downto 0);
   signal add_8_q_c : std_logic_vector(15 downto 0);
   signal reg_49_q_c : std_logic_vector(15 downto 0);
   signal reg_50_q_c : std_logic_vector(15 downto 0);

begin
      -- Connect signal to primary outputs
      PRI_OUT_0 <= mux2_5_q_c;
      PRI_OUT_1 <= reg_10_q_c;
      PRI_OUT_2 <= mux2_6_q_c;
      PRI_OUT_3 <= mux2_17_q_c;
      PRI_OUT_4 <= reg_13_q_c;
      PRI_OUT_5 <= reg_14_q_c;
      PRI_OUT_6 <= reg_15_q_c;
      PRI_OUT_7 <= reg_16_q_c;
      PRI_OUT_8 <= reg_17_q_c;
      PRI_OUT_9 <= reg_18_q_c;

      -- Subtracter (SUB_1) ---------------------------------------------------
      SUB_1: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_20_q_c,
         b => mux2_1_q_c,
         q => sub_1_q_c
      );
    

      -- Subtracter (SUB_2) ---------------------------------------------------
      SUB_2: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_19_q_c,
         b => reg_27_q_c,
         q => sub_2_q_c
      );
    

      -- Subtracter (SUB_3) ---------------------------------------------------
      SUB_3: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_12_q_c,
         b => reg_28_q_c,
         q => sub_3_q_c
      );
    

      -- Subtracter (SUB_4) ---------------------------------------------------
      SUB_4: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_18_q_c,
         b => reg_30_q_c,
         q => sub_4_q_c
      );
    

      -- Subtracter (SUB_5) ---------------------------------------------------
      SUB_5: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_6,
         b => reg_33_q_c,
         q => sub_5_q_c
      );
    

      -- Subtracter (SUB_6) ---------------------------------------------------
      SUB_6: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_15_q_c,
         b => mux2_16_q_c,
         q => sub_6_q_c
      );
    

      -- Subtracter (SUB_7) ---------------------------------------------------
      SUB_7: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_14_q_c,
         b => reg_34_q_c,
         q => sub_7_q_c
      );
    

      -- Subtracter (SUB_8) ---------------------------------------------------
      SUB_8: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_1,
         b => reg_35_q_c,
         q => sub_8_q_c
      );
    

      -- Subtracter (SUB_9) ---------------------------------------------------
      SUB_9: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_17_q_c,
         b => mux2_4_q_c,
         q => sub_9_q_c
      );
    

      -- Subtracter (SUB_10) --------------------------------------------------
      SUB_10: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_20_q_c,
         b => reg_16_q_c,
         q => sub_10_q_c
      );
    

      -- Subtracter (SUB_11) --------------------------------------------------
      SUB_11: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_36_q_c,
         b => reg_37_q_c,
         q => sub_11_q_c
      );
    

      -- Subtracter (SUB_12) --------------------------------------------------
      SUB_12: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_38_q_c,
         b => PRI_IN_0,
         q => sub_12_q_c
      );
    

      -- Subtracter (SUB_13) --------------------------------------------------
      SUB_13: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_26_q_c,
         b => reg_35_q_c,
         q => sub_13_q_c
      );
    

      -- Subtracter (SUB_14) --------------------------------------------------
      SUB_14: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_39_q_c,
         b => mux2_22_q_c,
         q => sub_14_q_c
      );
    

      -- Subtracter (SUB_15) --------------------------------------------------
      SUB_15: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_15_q_c,
         b => mux2_13_q_c,
         q => sub_15_q_c
      );
    

      -- Subtracter (SUB_16) --------------------------------------------------
      SUB_16: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_20_q_c,
         b => reg_40_q_c,
         q => sub_16_q_c
      );
    

      -- Subtracter (SUB_17) --------------------------------------------------
      SUB_17: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_12_q_c,
         b => reg_41_q_c,
         q => sub_17_q_c
      );
    

      -- Subtracter (SUB_18) --------------------------------------------------
      SUB_18: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_23_q_c,
         b => mux2_8_q_c,
         q => sub_18_q_c
      );
    

      -- Subtracter (SUB_19) --------------------------------------------------
      SUB_19: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_6,
         b => reg_42_q_c,
         q => sub_19_q_c
      );
    

      -- Subtracter (SUB_20) --------------------------------------------------
      SUB_20: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_10_q_c,
         b => reg_7_q_c,
         q => sub_20_q_c
      );
    

      -- Subtracter (SUB_21) --------------------------------------------------
      SUB_21: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_23_q_c,
         b => mux2_1_q_c,
         q => sub_21_q_c
      );
    

      -- Subtracter (SUB_22) --------------------------------------------------
      SUB_22: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_9_q_c,
         b => reg_40_q_c,
         q => sub_22_q_c
      );
    

      -- Subtracter (SUB_23) --------------------------------------------------
      SUB_23: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_22_q_c,
         b => mux2_11_q_c,
         q => sub_23_q_c
      );
    

      -- Subtracter (SUB_24) --------------------------------------------------
      SUB_24: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_14_q_c,
         b => reg_7_q_c,
         q => sub_24_q_c
      );
    

      -- Subtracter (SUB_25) --------------------------------------------------
      SUB_25: SUB
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_21_q_c,
         b => reg_43_q_c,
         q => sub_25_q_c
      );
    

      -- Adder (ADD_1) --------------------------------------------------------
      ADD_1: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_27_q_c,
         b => reg_38_q_c,
         q => add_1_q_c
      );
    

      -- Adder (ADD_2) --------------------------------------------------------
      ADD_2: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_44_q_c,
         b => reg_45_q_c,
         q => add_2_q_c
      );
    

      -- Adder (ADD_3) --------------------------------------------------------
      ADD_3: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_4,
         b => mux2_12_q_c,
         q => add_3_q_c
      );
    

      -- Adder (ADD_4) --------------------------------------------------------
      ADD_4: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_31_q_c,
         b => mux2_3_q_c,
         q => add_4_q_c
      );
    

      -- Adder (ADD_5) --------------------------------------------------------
      ADD_5: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_5_q_c,
         b => reg_44_q_c,
         q => add_5_q_c
      );
    

      -- Adder (ADD_6) --------------------------------------------------------
      ADD_6: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_46_q_c,
         b => reg_28_q_c,
         q => add_6_q_c
      );
    

      -- Adder (ADD_7) --------------------------------------------------------
      ADD_7: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_37_q_c,
         b => reg_46_q_c,
         q => add_7_q_c
      );
    

      -- Adder (ADD_8) --------------------------------------------------------
      ADD_8: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_46_q_c,
         b => mux2_20_q_c,
         q => add_8_q_c
      );
    

      -- Adder (ADD_9) --------------------------------------------------------
      ADD_9: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_6,
         b => reg_36_q_c,
         q => add_9_q_c
      );
    

      -- Adder (ADD_10) -------------------------------------------------------
      ADD_10: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_16_q_c,
         b => reg_47_q_c,
         q => add_10_q_c
      );
    

      -- Adder (ADD_11) -------------------------------------------------------
      ADD_11: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_17_q_c,
         b => mux2_6_q_c,
         q => add_11_q_c
      );
    

      -- Adder (ADD_12) -------------------------------------------------------
      ADD_12: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_15_q_c,
         b => reg_48_q_c,
         q => add_12_q_c
      );
    

      -- Adder (ADD_13) -------------------------------------------------------
      ADD_13: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_10_q_c,
         b => reg_32_q_c,
         q => add_13_q_c
      );
    

      -- Adder (ADD_14) -------------------------------------------------------
      ADD_14: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_7_q_c,
         b => reg_45_q_c,
         q => add_14_q_c
      );
    

      -- Adder (ADD_15) -------------------------------------------------------
      ADD_15: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_43_q_c,
         b => PRI_IN_1,
         q => add_15_q_c
      );
    

      -- Adder (ADD_16) -------------------------------------------------------
      ADD_16: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_31_q_c,
         b => reg_20_q_c,
         q => add_16_q_c
      );
    

      -- Adder (ADD_17) -------------------------------------------------------
      ADD_17: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_46_q_c,
         b => reg_49_q_c,
         q => add_17_q_c
      );
    

      -- Adder (ADD_18) -------------------------------------------------------
      ADD_18: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_12_q_c,
         b => reg_48_q_c,
         q => add_18_q_c
      );
    

      -- Adder (ADD_19) -------------------------------------------------------
      ADD_19: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => PRI_IN_5,
         b => mux2_10_q_c,
         q => add_19_q_c
      );
    

      -- Adder (ADD_20) -------------------------------------------------------
      ADD_20: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_50_q_c,
         b => reg_45_q_c,
         q => add_20_q_c
      );
    

      -- Adder (ADD_21) -------------------------------------------------------
      ADD_21: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_12_q_c,
         b => mux2_22_q_c,
         q => add_21_q_c
      );
    

      -- Adder (ADD_22) -------------------------------------------------------
      ADD_22: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_22_q_c,
         b => reg_47_q_c,
         q => add_22_q_c
      );
    

      -- Adder (ADD_23) -------------------------------------------------------
      ADD_23: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_14_q_c,
         b => reg_20_q_c,
         q => add_23_q_c
      );
    

      -- Adder (ADD_24) -------------------------------------------------------
      ADD_24: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => mux2_20_q_c,
         b => PRI_IN_7,
         q => add_24_q_c
      );
    

      -- Adder (ADD_25) -------------------------------------------------------
      ADD_25: ADD
      generic map (
         width_a => 16
      ) 
      port map (
         a => reg_17_q_c,
         b => mux2_9_q_c,
         q => add_25_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_1) --------------------------------------
      MUX2_1: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_24_q_c,
         b   => reg_25_q_c,
         sel => C_MUX2_1_SEL,
         q   => mux2_1_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_2) --------------------------------------
      MUX2_2: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_24_q_c,
         b   => PRI_IN_1,
         sel => C_MUX2_2_SEL,
         q   => mux2_2_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_3) --------------------------------------
      MUX2_3: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_22_q_c,
         b   => reg_30_q_c,
         sel => C_MUX2_3_SEL,
         q   => mux2_3_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_4) --------------------------------------
      MUX2_4: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_29_q_c,
         b   => reg_30_q_c,
         sel => C_MUX2_4_SEL,
         q   => mux2_4_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_5) --------------------------------------
      MUX2_5: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_7_q_c,
         b   => reg_1_q_c,
         sel => C_MUX2_5_SEL,
         q   => mux2_5_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_6) --------------------------------------
      MUX2_6: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_11_q_c,
         b   => mux2_25_q_c,
         sel => C_MUX2_6_SEL,
         q   => mux2_6_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_7) --------------------------------------
      MUX2_7: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_14_q_c,
         b   => reg_5_q_c,
         sel => C_MUX2_7_SEL,
         q   => mux2_7_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_8) --------------------------------------
      MUX2_8: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_5_q_c,
         b   => reg_7_q_c,
         sel => C_MUX2_8_SEL,
         q   => mux2_8_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_9) --------------------------------------
      MUX2_9: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => PRI_IN_8,
         b   => PRI_IN_3,
         sel => C_MUX2_9_SEL,
         q   => mux2_9_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_10) -------------------------------------
      MUX2_10: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_32_q_c,
         b   => mux2_3_q_c,
         sel => C_MUX2_10_SEL,
         q   => mux2_10_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_11) -------------------------------------
      MUX2_11: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_21_q_c,
         b   => reg_2_q_c,
         sel => C_MUX2_11_SEL,
         q   => mux2_11_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_12) -------------------------------------
      MUX2_12: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_16_q_c,
         b   => reg_21_q_c,
         sel => C_MUX2_12_SEL,
         q   => mux2_12_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_13) -------------------------------------
      MUX2_13: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_19_q_c,
         b   => mux2_23_q_c,
         sel => C_MUX2_13_SEL,
         q   => mux2_13_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_14) -------------------------------------
      MUX2_14: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_3_q_c,
         b   => reg_8_q_c,
         sel => C_MUX2_14_SEL,
         q   => mux2_14_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_15) -------------------------------------
      MUX2_15: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_9_q_c,
         b   => reg_34_q_c,
         sel => C_MUX2_15_SEL,
         q   => mux2_15_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_16) -------------------------------------
      MUX2_16: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_23_q_c,
         b   => PRI_IN_9,
         sel => C_MUX2_16_SEL,
         q   => mux2_16_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_17) -------------------------------------
      MUX2_17: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_11_q_c,
         b   => reg_4_q_c,
         sel => C_MUX2_17_SEL,
         q   => mux2_17_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_18) -------------------------------------
      MUX2_18: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_2_q_c,
         b   => reg_7_q_c,
         sel => C_MUX2_18_SEL,
         q   => mux2_18_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_19) -------------------------------------
      MUX2_19: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_20_q_c,
         b   => reg_22_q_c,
         sel => C_MUX2_19_SEL,
         q   => mux2_19_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_20) -------------------------------------
      MUX2_20: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_1_q_c,
         b   => reg_26_q_c,
         sel => C_MUX2_20_SEL,
         q   => mux2_20_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_21) -------------------------------------
      MUX2_21: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => reg_6_q_c,
         b   => mux2_18_q_c,
         sel => C_MUX2_21_SEL,
         q   => mux2_21_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_22) -------------------------------------
      MUX2_22: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => PRI_IN_2,
         b   => reg_31_q_c,
         sel => C_MUX2_22_SEL,
         q   => mux2_22_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_23) -------------------------------------
      MUX2_23: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => PRI_IN_9,
         b   => reg_19_q_c,
         sel => C_MUX2_23_SEL,
         q   => mux2_23_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_24) -------------------------------------
      MUX2_24: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => PRI_IN_6,
         b   => reg_9_q_c,
         sel => C_MUX2_24_SEL,
         q   => mux2_24_q_c
      );
    

      -- Multiplexor - 2 inputs (MUX2_25) -------------------------------------
      MUX2_25: MUX2
      generic map (
         width_a => 16
      ) 
      port map (
         a   => mux2_6_q_c,
         b   => reg_12_q_c,
         sel => C_MUX2_25_SEL,
         q   => mux2_25_q_c
      );
    

      -- Register (REG_1) -----------------------------------------------------
      REG_1: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_24_q_c,
         clk => CLK,
         q   => reg_1_q_c
      );
    

      -- Register (REG_2) -----------------------------------------------------
      REG_2: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_6_q_c,
         clk => CLK,
         q   => reg_2_q_c
      );
    

      -- Register (REG_3) -----------------------------------------------------
      REG_3: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_7_q_c,
         clk => CLK,
         q   => reg_3_q_c
      );
    

      -- Register (REG_4) -----------------------------------------------------
      REG_4: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_16_q_c,
         clk => CLK,
         q   => reg_4_q_c
      );
    

      -- Register (REG_5) -----------------------------------------------------
      REG_5: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_20_q_c,
         clk => CLK,
         q   => reg_5_q_c
      );
    

      -- Register (REG_6) -----------------------------------------------------
      REG_6: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_20_q_c,
         clk => CLK,
         q   => reg_6_q_c
      );
    

      -- Register (REG_7) -----------------------------------------------------
      REG_7: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_4_q_c,
         clk => CLK,
         q   => reg_7_q_c
      );
    

      -- Register (REG_8) -----------------------------------------------------
      REG_8: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_6_q_c,
         clk => CLK,
         q   => reg_8_q_c
      );
    

      -- Register (REG_9) -----------------------------------------------------
      REG_9: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_1_q_c,
         clk => CLK,
         q   => reg_9_q_c
      );
    

      -- Register (REG_10) ----------------------------------------------------
      REG_10: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_8_q_c,
         clk => CLK,
         q   => reg_10_q_c
      );
    

      -- Register (REG_11) ----------------------------------------------------
      REG_11: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_10_q_c,
         clk => CLK,
         q   => reg_11_q_c
      );
    

      -- Register (REG_12) ----------------------------------------------------
      REG_12: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_5_q_c,
         clk => CLK,
         q   => reg_12_q_c
      );
    

      -- Register (REG_13) ----------------------------------------------------
      REG_13: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_13_q_c,
         clk => CLK,
         q   => reg_13_q_c
      );
    

      -- Register (REG_14) ----------------------------------------------------
      REG_14: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_21_q_c,
         clk => CLK,
         q   => reg_14_q_c
      );
    

      -- Register (REG_15) ----------------------------------------------------
      REG_15: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_25_q_c,
         clk => CLK,
         q   => reg_15_q_c
      );
    

      -- Register (REG_16) ----------------------------------------------------
      REG_16: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_4_q_c,
         clk => CLK,
         q   => reg_16_q_c
      );
    

      -- Register (REG_17) ----------------------------------------------------
      REG_17: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_22_q_c,
         clk => CLK,
         q   => reg_17_q_c
      );
    

      -- Register (REG_18) ----------------------------------------------------
      REG_18: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_5_q_c,
         clk => CLK,
         q   => reg_18_q_c
      );
    

      -- Register (REG_19) ----------------------------------------------------
      REG_19: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_24_q_c,
         clk => CLK,
         q   => reg_19_q_c
      );
    

      -- Register (REG_20) ----------------------------------------------------
      REG_20: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_18_q_c,
         clk => CLK,
         q   => reg_20_q_c
      );
    

      -- Register (REG_21) ----------------------------------------------------
      REG_21: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_3_q_c,
         clk => CLK,
         q   => reg_21_q_c
      );
    

      -- Register (REG_22) ----------------------------------------------------
      REG_22: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_9_q_c,
         clk => CLK,
         q   => reg_22_q_c
      );
    

      -- Register (REG_23) ----------------------------------------------------
      REG_23: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_2_q_c,
         clk => CLK,
         q   => reg_23_q_c
      );
    

      -- Register (REG_24) ----------------------------------------------------
      REG_24: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_17_q_c,
         clk => CLK,
         q   => reg_24_q_c
      );
    

      -- Register (REG_25) ----------------------------------------------------
      REG_25: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_11_q_c,
         clk => CLK,
         q   => reg_25_q_c
      );
    

      -- Register (REG_26) ----------------------------------------------------
      REG_26: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_7_q_c,
         clk => CLK,
         q   => reg_26_q_c
      );
    

      -- Register (REG_27) ----------------------------------------------------
      REG_27: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_13_q_c,
         clk => CLK,
         q   => reg_27_q_c
      );
    

      -- Register (REG_28) ----------------------------------------------------
      REG_28: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_19_q_c,
         clk => CLK,
         q   => reg_28_q_c
      );
    

      -- Register (REG_29) ----------------------------------------------------
      REG_29: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_11_q_c,
         clk => CLK,
         q   => reg_29_q_c
      );
    

      -- Register (REG_30) ----------------------------------------------------
      REG_30: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_17_q_c,
         clk => CLK,
         q   => reg_30_q_c
      );
    

      -- Register (REG_31) ----------------------------------------------------
      REG_31: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_18_q_c,
         clk => CLK,
         q   => reg_31_q_c
      );
    

      -- Register (REG_32) ----------------------------------------------------
      REG_32: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_21_q_c,
         clk => CLK,
         q   => reg_32_q_c
      );
    

      -- Register (REG_33) ----------------------------------------------------
      REG_33: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_14_q_c,
         clk => CLK,
         q   => reg_33_q_c
      );
    

      -- Register (REG_34) ----------------------------------------------------
      REG_34: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_14_q_c,
         clk => CLK,
         q   => reg_34_q_c
      );
    

      -- Register (REG_35) ----------------------------------------------------
      REG_35: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_19_q_c,
         clk => CLK,
         q   => reg_35_q_c
      );
    

      -- Register (REG_36) ----------------------------------------------------
      REG_36: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_15_q_c,
         clk => CLK,
         q   => reg_36_q_c
      );
    

      -- Register (REG_37) ----------------------------------------------------
      REG_37: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_10_q_c,
         clk => CLK,
         q   => reg_37_q_c
      );
    

      -- Register (REG_38) ----------------------------------------------------
      REG_38: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_3_q_c,
         clk => CLK,
         q   => reg_38_q_c
      );
    

      -- Register (REG_39) ----------------------------------------------------
      REG_39: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_22_q_c,
         clk => CLK,
         q   => reg_39_q_c
      );
    

      -- Register (REG_40) ----------------------------------------------------
      REG_40: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_9_q_c,
         clk => CLK,
         q   => reg_40_q_c
      );
    

      -- Register (REG_41) ----------------------------------------------------
      REG_41: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_12_q_c,
         clk => CLK,
         q   => reg_41_q_c
      );
    

      -- Register (REG_42) ----------------------------------------------------
      REG_42: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_16_q_c,
         clk => CLK,
         q   => reg_42_q_c
      );
    

      -- Register (REG_43) ----------------------------------------------------
      REG_43: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_23_q_c,
         clk => CLK,
         q   => reg_43_q_c
      );
    

      -- Register (REG_44) ----------------------------------------------------
      REG_44: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_1_q_c,
         clk => CLK,
         q   => reg_44_q_c
      );
    

      -- Register (REG_45) ----------------------------------------------------
      REG_45: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_12_q_c,
         clk => CLK,
         q   => reg_45_q_c
      );
    

      -- Register (REG_46) ----------------------------------------------------
      REG_46: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_15_q_c,
         clk => CLK,
         q   => reg_46_q_c
      );
    

      -- Register (REG_47) ----------------------------------------------------
      REG_47: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_23_q_c,
         clk => CLK,
         q   => reg_47_q_c
      );
    

      -- Register (REG_48) ----------------------------------------------------
      REG_48: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_8_q_c,
         clk => CLK,
         q   => reg_48_q_c
      );
    

      -- Register (REG_49) ----------------------------------------------------
      REG_49: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => sub_25_q_c,
         clk => CLK,
         q   => reg_49_q_c
      );
    

      -- Register (REG_50) ----------------------------------------------------
      REG_50: REG
      generic map (
         width_a => 16
      ) 
      port map (
         d   => add_2_q_c,
         clk => CLK,
         q   => reg_50_q_c
      );
    
end architecture CIRCUIT_arch;