-- ------------------------------------------------------------------------- --
--                           Component library                               --
-- ------------------------------------------------------------------------- --

-- ############################################################################
-- ############################################################################
--                                   ADD              
-- ############################################################################
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity ADD is
   generic (
      width_a : positive);  
   port(
      -- Inputs
      a : in std_logic_vector(width_a - 1 downto 0);
      b : in std_logic_vector(width_a - 1 downto 0);
      -- Outputs
      q : out std_logic_vector(width_a - 1 downto 0)
   );
end entity ADD;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture ADD_arch of ADD is
begin
   process(a, b)
   begin
      q <= a + b;
   end process;
end architecture ADD_arch;

-- ############################################################################
-- ############################################################################
--                                   SUB              
-- ############################################################################
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity SUB is
   generic (
      width_a : positive);  
   port(
      -- Inputs
      a : in std_logic_vector(width_a - 1 downto 0);
      b : in std_logic_vector(width_a - 1 downto 0);
      -- Outputs
      q : out std_logic_vector(width_a - 1 downto 0)
   );
end entity SUB;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture SUB_arch of SUB is
begin
   process(a, b)
   begin
      q <= a - b;
   end process;
end architecture SUB_arch;

-- ############################################################################
-- ############################################################################
--                                   MUL              
-- ############################################################################
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity MUL is
   generic (
      width_a : positive;
      width_b : positive);  
   port(
      -- Inputs
      a : in  std_logic_vector(width_a - 1 downto 0);
      b : in  std_logic_vector(width_a - 1 downto 0);
      -- Outputs
      q : out std_logic_vector(width_b - 1 downto 0)
   );
end entity MUL;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture MUL_arch of MUL is
begin
   process(a, b)
   begin
      q <= a * b;
   end process;
end architecture MUL_arch;

-- ############################################################################
-- ############################################################################
--                                   MUX2             
-- ############################################################################
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity MUX2 is
   generic (
      width_a : positive);  
   port(
      -- Inputs
      a   : in  std_logic_vector(width_a - 1 downto 0);
      b   : in  std_logic_vector(width_a - 1 downto 0);
      sel : in  std_logic;
      -- Outputs
      q   : out std_logic_vector(width_a - 1 downto 0)
   );
end entity MUX2;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture MUX2_arch of MUX2 is
begin

   process(sel, a, b)
   begin
      case sel is
         when '0' => q <= a;
         when '1' => q <= b;
         when others => NULL;
      end case;
   end process;

end architecture MUX2_arch;

-- ############################################################################
-- ############################################################################
--                                   REG              
-- ############################################################################
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

-- ----------------------------------------------------------------------------
--                        Entity declaration
-- ----------------------------------------------------------------------------
entity REG is
   generic (
      width_a : positive);  
   port(
      -- Inputs
      d   : in  std_logic_vector(width_a - 1 downto 0);
      clk : in  std_logic;
      -- Outputs
      q   : out std_logic_vector(width_a - 1 downto 0)
   );
end entity REG;

-- ----------------------------------------------------------------------------
--                      Architecture declaration
-- ----------------------------------------------------------------------------
architecture REG_arch of REG is
begin

   -- register reg ------------------------------
   process(clk)
   begin
      if (clk'event AND clk='1') then
         q <= d;
      end if;
   end process;

end architecture REG_arch;