| Summary of Results |
In the field of evolvable hardware, evolutionary algorithms (EA) are used to generate configurations for reconfigurable chips that can dynamically alter the functionality and physical connections of their circuits. Research in the field of evolvable hardware can be split into the two related areas of evolutionary hardware design and adaptive hardware. While evolutionary hardware design is the use of EAs for creating innovative (and sometimes patentable) physical designs, the goal of adaptive hardware is to endow physical systems with some adaptive characteristics in order to allow them to operate successfully in a changing environment or under presence of faults.
Here we survey our contributions to the field. Most research papers can be downloaded.
Monographs
- Sekanina, L: Evolvable Components. Natural Computing Series, Springer-Verlag, 2004
- Sekanina L., Vašíček Z., Růžička R., Bidlo M., Jaroš J., Švenda P.: Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Academia Praha 2009, 328 p.
- Bidlo M.: Evolutionary Design of Generic Structures Using Instruction-Based Development. Brno University of Technology, 2010, 124 p.
- Gajda Z., Sekanina L.: Recent Advances in Evolutionary Synthesis and Optimization of Ordinary and Polymorphic Circuits. Brno University of Technology, 2011, 117 p.
PhD thesis
- Gajda Z.: Evolutionary Approach to Synthesis and Optimization of Ordinary and Polymorphic Circuits. FIT BUT 2011, 92 p.
- Bidlo M.: Evolutionary Design of Generic Structures Using Instruction-Based Development. FIT BUT 2009, 124 p. link
- Sekanina L: Component Approach to Evolvable Systems. FIT BUT 2002, 132 p. link (extended version published as Evolvable components by Springer)
Evolutionary Circuit Design
We have applied evolutionary design to evolve various circuits, in some cases evolved circuits are better than the best known conventional solutions (according to given critera). One utility model was granted in 2009 and a patent application was submitted (see Nonlinear image filter).Image Filters
Evolved filters exhibit good filtering properties while the implementation cost (e.g. in the FPGA) is very low when compared to conventional solutions such as median-based filters.- Impulse burst noise: AHS 2009 (with U. of Oslo), DATE 2010, AHS 2011, CEC 2011
- Salt and Pepper Noise (high intensity): FPL 2007, ICES 2007
- Shot noise, edge detectors: CEC 2011, DDECS 2002 (Best Paper Award), NASA EH 2003
- Gaussian noise, random noise: EvoIASP 2002
- Dynamic noise: Mendel 2002
- see also Evolvable Components, Springer (Merit Award at Humies 2004)
- Reference implementations of conventional median filters DDECS 2008
Evolutionary Logic Synthesis
- Formal verification in the fitness function for evolution of complex circuits: GPEM 12(3) 2011, DATE 2011, (Silver Medal at Humies 2011)
- Cartesian genetic programming really beats conventional synthesis tools in case of "hard to synthesize" circuits: DDECS 2010 (with FIT CVUT Prague)
- Small combinational circuits: Elektrorevue 2004, GECCO 2007, ICES 2010, GECCO 2010
Benchmark Circuits for Diagnostics CAD tools
We evolved benchmark circuits with predefined testability and with the size of 1 Mgates.- NASA EH 2005, DDECS 2006, TODAES 13(3), 2008 (Silver Medal at Humies 2008)
- Download FITTest_BENCH06 Benchmarks
Image Recognition (with J. Torresen, University of Oslo)
Evolutionary Image Compression (with Ruben Salvador, Universidad Politécnica de Madrid)
- Evolution of Wavelet Transforms for Embedded Systems: EURASIP Journal on Advances in Signal Processing 2011, SPIE VLSI 2011, AHS 2010, DSD 2010, DCIS 2010
- Evolution of nonlinear predictors: Nostradamus 1999, FPL 2000
Other Circuits
- Multiple Constant Multipliers: ICES 2008
- Gate-level evolution of FIR and IIR filters: EvoHOT 2006
- Transistor-level evolution: ICES 2008
- Median circuits: EvoHOT 2004
- Module Selection Problem in High-Level Synthesis: Mendel 2002
- Branch Predictors: GECCO 2008
FPGA Accelerators for Evolutionary Design
We have developed the concept of Virtual Reconfigurable Circuits (VRC) for real-world applications of evolvable hardware in FPGAs.- Accelerator for image filter evolution - speedup 170 wrt PC (EA in PowerPC, multiple VRCs): MEMICS 2009 (Best Paper Award), CaI 29(6), 2010
- Accelerator for image filter evolution - speedup 44 wrt PC (EA in PowerPC, 1 VRC): IJICA 1(1), 2007, AHS 2007 (analysis of mutation operators and pseudorandom generators)
- Accelerator of CGP (EA in PowerPC, 1 VRC): EuroGP 2008 (Best Paper Award Nomination)
- Accelerator for image filter evolution (EA in HW, 1 VRC): Hindawi's book chapter, ICES 2005
- Accelerator for sorting network evolution (EA in HW, 1 VRC): ICES 2005
- Accelerator for combinational circuit evolution (EA in HW, 1 VRC): DDECS 2004, NASA EH 2004, CaI 23(5), 2004
- Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures: EvoHOT 2008 (Best Paper Award Nomination)
- Evolutionary Functional Recovery in Virtual Reconfigurable Circuits: ACM JETCS 3(2), 2007, ACM CF 2006
- Evolvable IP cores: NASA EH 2003
- Introduction of VRCs: ICES 2003 (Best Presentation Award), DDECS 2000
- see also Evolvable Components (Springer)
- Processing Array: AHS 2011a, AHS 2011b
- Fault tolerance issues: Reconfig 2011
GPU Accelerators for Evolutionary Design
Polymorphic Electronics
We have devoloped first reconfigurable polymorphic ASIC (REPOMO32), implemented several methods for synthesis of polymorphic circuits and proposed several new applications of polymorphic electronics.- Polymorphic ASIC REPOMO32: WEAH 2009 (analysis of various architectures: AHS 2008, IASTED CI 2006
- Synthesis of polymorphic circuits: EvoHOT 2005 (Best Paper Award), DDECS 2005, CEC 2006, CEC 2009, JMVLSC 17(6) 2011, DATE 2012
- Polymorphic image filters: DATE 2012
- Polymorphic FIR filters: AHS 2009
- Self-checking circuits: DDECS 2007, ICES 2007
- Reduction of test vectors volume: DDECS 2008, JUC 4(2), 2008, ICES 2010
- Analysis and measurement of polymorphic gates: AHS 2006, DDECS 2006, ECS 2007, IOLTS 2008, DDECS 2010, in high temperatures DDECS 2011, DSD 2011
- Polymorphic Cellular Automata and Self-replication: JCA 6(4) 2011
Evolutionary Design of Protocols (with P. Svenda and V. Matyas, FI MU Brno)
- Evolutionary Design of Secrecy Amplification Protocols for Wireless Sensor Networks: WiSec 2009, EuroGP 2012
Evolution using FPTA-2 chip (with NASA JPL)
- Low temperature experiments: ICES 2005, Springer's book chapter 2006
- Flip-flops: EH 2005
- Controllable oscillators: ICES 2005
Development in Evolutionary Design
We have introduced non-trivial mappings between genotypes and phenotypes to overcome scalability problems of evolutionary design. One approach uses an instruction-based development, another one cellular automata.- Cellular automata-based development: ICES 2008, AHS 2008, CEC 2009, GECCO 2009, AHS 2009, ICES 2010
- Growing multipliers: AHS 2007, ICES 2007, JKBIES 12(3) 2008
- Growing arbitrarily large sorting networks: SOFSEM 2004, GENP 6(3) 2005 (Honorable mention at Humies 2005)
- Growing polymorphic circuits: GECCO 2005 - workshop
- A formal proof that evolved constuctor for sorting networks is general: TECT 15(10), 2006
- The role of environment: Mendel 2010
Cartesian Genetic Programming: theory etc.
- Miller J. F. (ed.): Cartesian Genetic Programming, Springer 2011 - see chapters on circuit evolution, image processing and CGP in FPGA.
- Coevolution in CGP: EuroGP 2012
- Evolution of iterative algorithms: KES 2011
- A new selection strategy: ICES 2010, GECCO 2010
- ALPS in CGP: EuroGP 2009
- Does crossover work in CGP? EuroGP 2007
Cellular Platforms
- Fault tolerance in cellular systems: IOLTS 2000, UC 2011, NaBIC 2011
- Parallel GA for CellMatrix: ESM 2001
Philosophical aspects, theory etc.
- Evolved Computing Devices and the Implementation Problem: Minds and machines 17(3), 2007, KUZ 2007 (in Czech)
- Evolvable systems - models and super-Turing behaviors: JNC 3(3), 2004, EuroGP 2003, E-ISCI 2002
- see also Evolvable Components (Springer)
Traffic Modelling and Prediction
- CA-based Microscopic Traffic Simulation: IV 2011
- GPU accelerators: Mendel 2011
Survey papers
- Evolvable Hardware and evolutionary circuit design: ECBS 2004, AHS 2006, GECCO 2007, JAMRIS 3(2), 2009, UC 2009, GECCO 2011, SPIE VLSI 2011
- In Czech: Elektrorevue 1999, Vesmir 81(7) 2002, Vesmir 84(1) 2005, Automa 1/2010, Umelá inteligencia a kognitívna veda 2010
Last update: Feb 8, 2012