research outcomes/past projects

• We have utilized a simple developmental scheme to evolve arbitrarily large digital circuits. In case of sorting networks a novel scalable solution was discovered. In other cases conventional approaches were re-discovered. Examples include:
  • sorting and median networks
  • adders
  • parity circuits
• The idea of polymorphic electronics was discovered by JPL's evolvable hardware group. We have used evolutionary algorithms to design gate-level polymorphic circuits (e.g. adder/multiplier circuit etc.). We have applied a simple developmental scheme to evolve arbitrarily large polymorphic sorting networks and parity circuits, see publications.
• See animations of the evolutionary circuit design (multipliers, dividers, gate-level filters) at Z. Vasicek's pages.
• Complete hardware implementations of evolvable systems on FPGAs at the level of IP core developed, see publications. We used COMBO6 card. The main advantage of this approach is that the evolution is much faster than the evolution at PC (usually 40-100 times). The complete design occupies a part of Xilinx Virtex II FPGA and operate at 50/100MHz. Examples include:
  • Evolvable combinational unit (6 inputs, 6 outputs)
  • Evolvable image filters
  • Evolvable sorting networks
  
  
• New tools for evolutionary circuit design.
  
• Evolutionary design of benchmark circuits - see an example of the evolved 50-component circuit with the required testability properties.
  
• Evolutionary design of median circuits - we evolved median circuits up to 25 inputs, see publications.
  
• Development for evolvable hardware - we evolved constructors (programs) for designing arbitrarily large median and sorting networks, see publications.
  
• We developed a tool for the automatic design of virtual reconfigurable circuits from a specification given in a text file (like vroconfig.txt). Our software is able to generate a simulator (C++ files) as well as VHDL files for synthesis of the virtual reconfigurable circuit. The simulator (C++ files) can directly be utilized to evaluate the chromosomes produced by an evolutionary algorithm. The virtual reconfigurable circuit is organized in the style of Miller's Cartesian Genetic Programming. An example of the virtual reconfigurable circuit:
  
• Formal approach to evolvable machines and the computational power of evolvable machines. Do you know that an evolvable system can not be simulated by the Turing machine (under some assumptions)? See Evolvable Components.
• Evolutionary design of (testable) digital circuits. We evolved a plenty of interesting circuits for image preprocessing. See below a figure taken from the design tool. The circuits were awarded at the GECCO Human competitive results competition 2004.
  
• image compression using evolvable hardware. See below the figure taken from the design tool.