#what to generate: SOFTWARE -> C code, HARDWARE -> VHDL code
SOFTWARE: 2;
HARDWARE;

#number of rows
ROW: 2;

#number of columns
COL: 2;

#number of bits
BIT: 4;

#number of inputs
INPUT: 4;

#l-back
L-BACK: {1};

#connection of CFBs to inputs (0 - only CFB where COL < L-BACK; otherwise - all CFB) 
INPUT2ALL: 0;

#number of CFBs
CFB: 4;

#number of outputs {subrange} {output CFB}
OUTPUT: 2 {2..3} {2, 3};

#number of functions in CFB
NUM-FCI: 8;

#number of definitions of function sets
DEF-FCI: 1;

#variables for functions, the last one is the output variable
VAR-FCI: {"a","b","c"};

#defined functions in C code (a, b - input variables) (c - output variable)
FCE:0: {ALL}, {
{0: "c = a;":0           :VHDL:"c <= a;"},
{1: "c = b;": 1          :VHDL:"c <= b;"},
{2: "c = a && b;": 0:1   :VHDL:"c <= a and b;"},
{3: "c = a || b;": 0:1   :VHDL:"c <= a or b;"},
{4: "c = !(a && b);": 0:1:VHDL:"c <= not (a and b);"},
{5: "c = !(a || b);": 0:1:VHDL:"c <= not (a or b);"},
{6: "c = a + b;": 0:1    :VHDL:"c <= a + b;"},
{7: "c = a - b;": 0:1    :VHDL:"c <= a - b;"}
};