Prof. Ing. Lukás Sekanina, Ph.D.

2012Korcek, P., Sekanina, L., Fucík, O.: Calibration of Traffic Simulation Models Using Vehicle Travel Times, In: Cellular Automata, 11th International Conference on Cellular Automata for Research and Industry, Berlin, DE, Springer, 2012, s. 1-10
 Kotásek, Z., Bouda, J., Cerná, I., Sekanina, L., Vojnar, T., Antos, D. (editors): Mathematical and Engineering Methods in Computer Science, 7th International Doctoral Workshop, Revised Selected Papers, Berlin, DE, Springer, 2012, s. 215, ISBN 978-3-642-25928-9
 Sekanina, L., Salajka, V.: Towards New Applications of Multi-Function Logic: Image Multi-Filtering, In: Proc. of the 2012 Design, Automation and Test in Europe, Dresden, DE, EDAA, 2012, s. 1-4, ISBN 978-3-9810801-8-6
 Sekanina, L., Vasícek, Z.: A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits, In: Proc. of the 2012 Design, Automation and Test in Europe, Dresden, DE, EDAA, 2012, s. 1-6, ISBN 978-3-9810801-8-6
 Smolka, T., Svenda, P., Sekanina, L., Matyás, V.: Evolutionary Design of Message Efficient Secrecy Amplification Protocols, In: Proc. of the 15th European Conference on Genetic Programming, Heidelberg, DE, Springer, 2012, s. 194-205, ISBN 978-3-642-29138-8
 Sikulová, M., Sekanina, L.: Coevolution in Cartesian Genetic Programming, In: Proc. of the 15th European Conference on Genetic Programming, Heidelberg, DE, Springer, 2012, s. 182-193, ISBN 978-3-642-29138-8
2011Gajda, Z., Sekanina, L.: On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits, In: Journal of Multiple-Valued Logic and Soft Computing, roc. 17, c. 6, 2011, Philadelphia, US, s. 607-631, ISSN 1542-3980
 Gajda, Z., Sekanina, L.: Recent Advances in Evolutionary Synthesis and Optimization of Ordinary and Polymorphic Circuits, Brno, CZ, FIT VUT, 2011, s. 111, ISBN 978-80-214-4417-1
 Korcek, P., Sekanina, L., Fucík, O.: A Scalable Cellular Automata Based Microscopic Traffic Simulation, In: Proceedings of the IEEE Intelligent Vehicles Symposium 2011 (IV11), Baden-Baden, DE, IEEE ITSS, 2011, s. 13-18, ISBN 978-1-4577-0889-3
 Korcek, P., Sekanina, L., Fucík, O.: A Scalable Cellular Automata Based Microscopic Traffic Simulation, 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2011, s. 1, ISBN 978-80-214-4305-1
 Korcek, P., Sekanina, L., Fucík, O.: Cellular automata based traffic simulation accelerated on GPU, In: Proceedings of the 17th International Conference on Soft Computing (MENDEL2011), Brno, CZ, ÚAI FSI VUT, 2011, s. 395-402, ISBN 978-80-214-4302-0
 Korcek, P., Sekanina, L., Fucík, O.: Microscopic traffic simulation using CUDA, In: Advanced Computer Architecture and Compilation for High-Performace and Embedded Systems (ACACES 2011) Poster Abstracts, Fiuggi, IT, Academia Press, 2011, s. 207-210, ISBN 978-90-382-1798-7
 Minarík, M., Sekanina, L.: Evolution of Iterative Formulas Using Cartesian Genetic Programming, In: Lecture Notes in Computer Science, roc. 2011, c. 6881, DE, s. 11-20, ISSN 0302-9743
 Otero, A., Salvador, R., Mora, J., De, l., T., E., Riesgo, T., Sekanina, L.: A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems, In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2011, s. 336-343, ISBN 978-1-4577-0599-1
 Ruzicka, R., Simek, V., Sekanina, L.: Behavior of CMOS Polymorphic Circuits in High Temperature Environment, In: Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, DE, IEEE CS, 2011, s. 447-452, ISBN 978-1-4244-9753-9
 Salvador, R., Moreno, F., Riesgo, T., Sekanina, L.: Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems, In: EURASIP Journal on Advances in Signal Processing, roc. 2011, c. 2011, US, s. 1-20, ISSN 1687-6172
 Salvador, R., Otero, A., Mora, J., De, l., T., E., Riesgo, T., Sekanina, L.: Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support, In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2011, s. 184-191, ISBN 978-1-4577-0599-1
 Salvador, R., Otero, A., Mora, J., De, l., T., E., Sekanina, L., Riesgo, T.: Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems, In: Proc. of the 2011 International Conference on ReConFigurable Computing and FPGAs, Los Alamitos, US, IEEE CS, 2011, s. 164-169, ISBN 978-0-7695-4551-6
 Salvador, R., Vidal, A., Moreno, F., Riesgo, T., Sekanina, L.: Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems, In: VLSI Circuits and Systems V, Bellingham, US, SPIE, 2011, s. 1-13, ISBN 978-0-8194-8656-1
 Sekanina, L., Harding, S., L., Banzhaf, W., Kowaliw, T.: Image Processing and CGP, Cartesian Genetic Programming, Berlin, DE, Springer, 2011, s. 181-215, ISBN 978-3-642-17309-7
 Sekanina, L., Komenda, T.: Global Control in Polymorphic Cellular Automata, In: Journal of Cellular Automata, roc. 6, c. 4, 2011, Philadelphia, US, s. 301-321, ISSN 1557-5969
 Sekanina, L., Vasícek, Z.: CGP Acceleration Using Field-Programmable Gate Arrays, Cartesian Genetic Programming, Berlin, DE, Springer, 2011, s. 217-230, ISBN 978-3-642-17309-7
 Sekanina, L., Walker, J., A., Kaufmann, P., Platzner, M.: Evolution of Electronic Circuits, Cartesian Genetic Programming, Berlin, DE, Springer, 2011, s. 125-179, ISBN 978-3-642-17309-7
 Sekanina, L.: Evolution of digital circuits (Tutorial), In: Proceedings of the 2011 GECCO conference companion on Genetic and evolutionary computation, New York, US, ACM, 2011, s. 1343-1359, ISBN 978-1-4503-0690-4
 Sekanina, L.: Evolutionary hardware design (Invited Paper), In: VLSI Circuits and Systems V, Bellingham, US, SPIE, 2011, s. 1-11, ISBN 978-0-8194-8656-1
 Vasícek, Z., Bidlo, M., Sekanina, L., Glette, K.: Evolutionary Design of Efficient and Robust Switching Image Filters, In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2011, s. 192-199, ISBN 978-1-4577-0599-1
 Vasícek, Z., Sekanina, L.: A Global Postsynthesis Optimization Method for Combinational Circuits, In: Proc. of the Design, Automation and Test in Europe DATE 2011, Grenoble, FR, EDAA, 2011, s. 1525-1528, ISBN 978-3-9810801-7-9
 Vasícek, Z., Sekanina, L.: Evolutionary Optimization of Complex Digital Circuits, In: 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2011, s. 1, ISBN 978-80-214-4305-1
 Vasícek, Z., Sekanina, L.: Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware, In: Genetic Programming and Evolvable Machines, roc. 12, c. 3, 2011, Berlin, DE, s. 305-327, ISSN 1389-2576
 Zaloudek, L., Sekanina, L.: Increasing Fault-Tolerance in Cellular-Based Systems, In: Lecture Notes in Computer Science, roc. 2011, c. 6714, DE, s. 234-245, ISSN 0302-9743
2010Bidlo, M., Sekanina, L.: On Impact of Environment on the Complexity Generated by Evolutionary Development, In: MENDEL 2010 - 16th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2010, s. 501-508, ISBN 978-80-214-4120-0
 Fiser, P., Schmidt, J., Vasícek, Z., Sekanina, L.: On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming, In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, s. 346-351, ISBN 978-1-4244-6610-8
 Gajda, Z., Sekanina, L.: An Efficient Selection Strategy for Digital Circuit Evolution, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2010, s. 13-24, ISBN 978-3-642-15322-8
 Gajda, Z., Sekanina, L.: When Does Cartesian Genetic Programming Minimize the Phenotype Size Implicitly?, In: Proceeding of Genetic and Evolutionary Computation Conference, GECCO 2010, New York, US, ACM, 2010, s. 983-984, ISBN 978-1-4503-0072-8
 Korcek, P., Sekanina, L., Fucík, O.: Towards Scalable and Accurate Microscopic Traffic Simulation Using Advanced Cellular Automata Based Models, In: Proceedings of the 13th International IEEE Conference on Intelligent Transportation Systems Workshops, Madeira Island, PT, IEEE ITSS, 2010, s. 27-35, ISBN 978-972-8822-20-0
 Salvador, R., Moreno, F., Riesgo, T., Sekanina, L.: Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems, In: Proc. of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2010, s. 177-184, ISBN 978-1-4244-5888-2
 Salvador, R., Moreno, F., Riesgo, T., Sekanina, L.: High level validation of an optimization algorithm for the implementation of adaptive Wavelet Transforms in FPGAs, In: Proc. of 13th Euromicro Conference on Digital System Design, Los Alamitos, US, IEEE CS, 2010, s. 96-103, ISBN 978-0-7695-4171-6
 Salvador, R., Moreno, F., Riesgo, T., Sekanina, L.: Implementation of bio-inspired adaptive wavelet transforms in FPGAs. Modelling, validation and profiling of the algorithm, In: Proceedings of the XXV Conference on Design of Circuits and Integrated Systems, Lanzarote, ES, IUCTC, 2010, s. 210-215, ISBN 978-84-693-7393-4
 Sekanina, L.: Evolucní návrh elektronických obvodu, In: Automa, roc. 2010, c. 1, CZ, s. 48-51, ISSN 1210-9592
 Sekanina, L.: Evolucní návrh hardware, Umelá inteligencia a kognitívna veda II, Bratislava, SK, Vyd. STU, 2010, s. 437-465, ISBN 978-80-227-3284-0
 Sekanina, L.: Evolutionary Circuit Design: Tutorial, In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, s. 5-5, ISBN 978-1-4244-6610-8
 Simácek, J., Sekanina, L., Starecek, L.: Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2010, s. 214-225, ISBN 978-3-642-15322-8
 Simek, V., Ruzicka, R., Sekanina, L.: On Analysis of Fabricated Polymorphic Circuits, In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, s. 281-284, ISBN 978-1-4244-6610-8
 Vasícek, Z., Sekanina, L., Bidlo, M.: A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations, In: DATE 2010: Design, Automation and Test in Europe, Dresden, DE, EDAA, 2010, s. 1731-1736, ISBN 978-3-9810801-6-2
 Vasícek, Z., Sekanina, L.: Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units, In: Computing and Informatics, roc. 29, c. 6, 2010, Bratislava, SK, s. 1359-1371, ISSN 1335-9150
 Zaloudek, L., Sekanina, L., Simek, V.: Accelerating Cellular Automata Evolution on Graphics Processing Units, In: International Journal on Advances in Software, roc. 3, c. 1, 2010, US, s. 294-303, ISSN 1942-2628
2009Gajda, Z., Sekanina, L.: Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming, In: Proc. of 2009 IEEE Congress on Evolutionary Computation, NA, US, IEEE CIS, 2009, s. 1599-1604, ISBN 978-1-4244-2958-5
 Negoita, M., Sekanina, L., Stoica, A.: Adaptive and evolvable hardware and systems: the state of the art and the prospectus for future development, In: Journal of Automation, Mobile Robotics and Intelligent Systems, roc. 3, c. 2, 2009, PL, s. 70-75, ISSN 1897-8649
 Sekanina, L., Ruzicka, R., Gajda, Z.: Polymorphic FIR Filters with Backup Mode Enabling Power Savings, In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, s. 43-50, ISBN 978-0-7695-3714-6
 Sekanina, L., Ruzicka, R., Vasícek, Z., Prokop, R., Fujcik, L.: REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware, In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware, Nashville, US, IEEE CIS, 2009, s. 39-46, ISBN 978-1-4244-2755-0
 Sekanina, L., Vasícek, Z., Ruzicka, R., Bidlo, M., Jaros, J., Svenda, P.: Evolucní hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojum, Praha, CZ, Academia, 2009, s. 328, ISBN 978-80-200-1729-1
 Sekanina, L.: Evolvable Hardware: From Applications to Implications for the Theory of Computation, In: Proc. of the 8th Int. Conference on Unconventional Computation, Berlin, DE, Springer, 2009, s. 24-36, ISBN 978-3-642-03744-3
 Svenda, P., Sekanina, L., Matyás, V.: Evolutionary Design of Secrecy Amplification Protocols for Wireless Sensor Networks, In: Proc. of the ACM Conference on Wireless Network Security, New York, US, ACM, 2009, s. 225-236, ISBN 978-1-60558-460-7
 Vasícek, Z., Bidlo, M., Sekanina, L., Torresen, J., Glette, K., Furuholmen, M.: Evolution of Impulse Bursts Noise Filters, In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, s. 27-34, ISBN 978-0-7695-3714-6
 Vasícek, Z., Sekanina, L.: Efficient Hardware Accelerator for Symbolic Regression Problems, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2009, s. 192-199, ISBN 978-80-87342-04-6
 Zaloudek, L., Sekanina, L., Simek, V.: GPU Accelerators for Evolvable Cellular Automata, In: Computation World: Future Computing, Service Computation, Adaptive, Content, Cognitive, Patterns, Athens, GR, IEEE, 2009, s. 533-537, ISBN 978-0-7695-3862-4
2008Hornby, G., S., Sekanina, L., Haddow, P., C. (editors): Proceedings of Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, s. 444, ISBN 978-3-540-85856-0
 Negoita, M., Sekanina, L., Stoica, A.: Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development, In: Knowledge-Based Intelligent Information and Engineering Systems, Berlin, DE, Springer, 2008, s. 310-318, ISBN 978-3-540-85566-8
 Pecenka, T., Sekanina, L., Kotásek, Z.: Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability, In: ACM Transactions on Design Automation of Electronic Systems, roc. 13, c. 3, 2008, US, s. 1-21, ISSN 1084-4309
 Ruzicka, R., Sekanina, L., Prokop, R.: Physical Demonstration of Polymorphic Self-checking Circuits, In: Proc. of the 14th IEEE Int. On-Line Testing Symposium, Los Alamitos, US, IEEE CS, 2008, s. 31-36, ISBN 978-0-7695-3264-6
 Sekanina, L., Mikusek, P.: Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures, In: Applications of Evolutionary Computing, Berlin, DE, Springer, 2008, s. 144-153, ISBN 978-3-540-78760-0
 Sekanina, L., Starecek, L., Kotásek, Z., Gajda, Z.: Polymorphic Gates in Design and Test of Digital Circuits, In: International Journal of Unconventional Computing, roc. 4, c. 2, 2008, Philadelphia, US, s. 125-142, ISSN 1548-7199
 Starecek, L., Sekanina, L., Kotásek, Z.: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, s. 255-258, ISBN 978-1-4244-2276-0
 Vasícek, Z., Capka, L., Sekanina, L.: Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit, In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2008, s. 3-10, ISBN 978-0-7695-3166-3
 Vasícek, Z., Sekanina, L.: Hardware Accelerators for Cartesian Genetic Programming, In: Eleventh European Conference on Genetic Programming, Berlin, DE, Springer, 2008, s. 230-241, ISBN 978-3-540-78670-2
 Vasícek, Z., Sekanina, L.: Novel Hardware Implementation of Adaptive Median Filters, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, s. 110-115, ISBN 978-1-4244-2276-0
 Vasícek, Z., Zádník, M., Sekanina, L., Tobola, J.: On Evolutionary Synthesis of Linear Transforms in FPGA, In: Evolvable Systems: From Biology > to > Hardware, Berlin, DE, Springer, 2008, s. 141-152, ISBN 978-3-540-85856-0
 Zaloudek, L., Sekanina, L.: Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, s. 320-331, ISBN 978-3-540-85856-0
2007Gajda, Z., Sekanina, L.: Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design, In: 2007 Genetic and Evolutionary Computation Conference, New York, US, ACM, 2007, s. 245-252, ISBN 9781595936974
 Sekanina, L., Martínek, T.: Evolving Image Operators Directly in Hardware, Genetic and Evolutionary Computation for Image Processing and Analysis, New York, US, Hindawi, 2007, s. 93-112, ISBN 978-977-454-001-1
 Sekanina, L.: Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates, In: 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Gliwice, PL, IEEE CS, 2007, s. 243-246, ISBN 1424411610
 Sekanina, L.: Evolution of Polymorphic Self-Checking Circuits, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, s. 186-197, ISBN 978-3-540-74625-6
 Sekanina, L.: Evolutionary Functional Recovery in Virtual Reconfigurable Circuits, In: ACM Journal on Emerging Technologies in Computing Systems, roc. 3, c. 2, 2007, US, s. 1-22, ISSN 1550-4832
 Sekanina, L.: Evolvable hardware: Tutorial, In: 2007 Genetic and Evolutionary Computational Conference, New York, US, ACM, 2007, s. 3627-3644, ISBN 9781595936981
 Sekanina, L.: Evolved Computing Devices and the Implementation Problem, In: Minds and Machines, roc. 17, c. 3, 2007, NL, s. 311-329, ISSN 0924-6495
 Sekanina, L.: Vztah mezi abstraktním a fyzickým výpoctem v kontextu evolucního návrhu, In: Kognice a umelý zivot VII, Opava, CZ, SLU, 2007, s. 305-310, ISBN 9788072484126
 Slaný, K., Sekanina, L.: Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP, In: Genetic Programming, 10th European Conference, EuroGP 2007, Berlin, DE, Springer, 2007, s. 311-320, ISBN 978-3-540-71602-0
 Starecek, L., Sekanina, L., Gajda, Z., Kotásek, Z., Prokop, R., Musil, V.: On Properties and Utilization of Some Polymorphic Gates, In: 6th Electronic Circuits and Systems Conference (ECS 2007), Bratislava, SK, FIIT STU, 2007, s. 77-81, ISBN 978-80-227-2697-9
 Vasícek, Z., Sekanina, L.: An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs, In: Proc. of 2007 International Conference on Field Programmable Logic and Applications, Los Alamitos, US, IEEE CS, 2007, s. 216-221, ISBN 1424410606
 Vasícek, Z., Sekanina, L.: An Evolvable Hardware System in Xilinx Virtex II Pro FPGA, In: International Journal of Innovative Computing and Applications , roc. 1, c. 1, 2007, Geneva, CH, s. 63-73, ISSN 1751-648X
 Vasícek, Z., Sekanina, L.: Evaluation of a New Platform For Image Filter Evolution, In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2007, s. 577-584, ISBN 076952866X
 Vasícek, Z., Sekanina, L.: Reducing the Area on a Chip Using a Bank of Evolved Filters, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, s. 222-232, ISBN 978-3-540-74625-6
2006Bidlo, M., Bidlo, R., Sekanina, L.: Designing a Novel General Sorting Network Constructor Using Artificial Evolution, In: TRANSACTIONS ON ENGINEERING, COMPUTING AND TECHNOLOGY, roc. 15, c. 10, 2006, Barcelona, ES, s. 85-90, ISBN 975-00803-4-3, ISSN 1305-5313
 Bidlo, M., Sekanina, L.: Prostredky pro podporu vzdelávání v oblasti biologií inspirovaných výpocetních systému, In: Pedagogický software 2006, Ceské Budejovice, CZ, spp, 2006, s. 81-83, ISBN 80-85645-56-4
 Pecenka, T., Kotásek, Z., Sekanina, L.: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, s. 285-289, ISBN 1424401844
 Pecenka, T., Strnadel, J., Kotásek, Z., Sekanina, L.: Testability Estimation Based on Controllability and Observability Parameters, In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06), Cavtat, HR, IEEE CS, 2006, s. 504-514, ISBN 0-7695-2609-8
 Ruzicka, R., Sekanina, L.: Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module, In: Proceedings of the Second IASTED International Conference on Computational Intelligence, Anaheim, US, ACTA Press, 2006, s. 237-241, ISBN 0-88986-602-3
 Sekanina, L., Martínek, T., Gajda, Z.: Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules, In: 2006 IEEE World Congress on Computational Intelligence, CA, US, IEEE CIS, 2006, s. 9676-9683, ISBN 0-7803-9489-5
 Sekanina, L., Starecek, L., Gajda, Z., Kotásek, Z.: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage, In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, Piscataway, US, IEEE CS, 2006, s. 186-193, ISBN 0-7695-2614-4
 Sekanina, L., Starecek, L., Kotásek, Z.: Novel Logic Circuits Controlled by Vdd, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, s. 85-86, ISBN 1424401844
 Sekanina, L., Vasícek, Z.: On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level, In: Applications of Evolutionary Computing, Berlin, DE, Springer, 2006, s. 344-355, ISBN 978-3-540-33237-4
 Sekanina, L.: Evolutionary Approach to the Implementation Problem, Brno, CZ, FIT VUT, 2006, s. 127
 Sekanina, L.: Evolutionary Design of Digital Circuits: Where Are Current Limits?, In: Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, Piscataway, US, IEEE CS, 2006, s. 171-178, ISBN 0-7695-2614-4
 Sekanina, L.: On Dependability of FPGA-Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits, In: Computing Frontiers 2006 Conference, New York, US, ACM, 2006, s. 221-228, ISBN 1595933026
 Zebulum, R., S., Keymeulen, D., Ramesham, R., Sekanina, L., Mao, J., Kumar, N., Stoica, A.: Characterization and Synthesis of Circuits at Extreme Low Temperatures, Evolvable Hardware, Berlin, DE, Springer, 2006, s. 161-172, ISBN 0-387-24386-0
2005Bidlo, M., Sekanina, L.: Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates, In: Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005, New York, US, ACM, 2005, s. 242-248, ISBN 1-59593-097-3
 Korenek, J., Sekanina, L.: Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2005, s. 46-55, ISBN 978-3-540-28736-0
 Martínek, T., Sekanina, L.: An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2005, s. 76-85, ISBN 978-3-540-28736-0
 Pecenka, T., Kotásek, Z., Sekanina, L., Strnadel, J.: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties, In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2005, s. 51-58, ISBN 0-7695-2399-4
 Sekanina, L., Bidlo, M.: Evolutionary Design of Arbitrarily Large Sorting Networks Using Development, In: Genetic Programming and Evolvable Machines, roc. 6, c. 3, 2005, Berlin, DE, s. 319-347, ISSN 1389-2576
 Sekanina, L., Zebulum, R., S.: Evolutionary discovering of the concept of the discrete state at the transistor level, In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2005, s. 73-78, ISBN 0-7695-2399-4
 Sekanina, L., Zebulum, R., S.: Intrinsic Evolution of Controllable Oscillators in FPTA-2, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2005, s. 98-107, ISBN 978-3-540-28736-0
 Sekanina, L.: Design Methods for Polymorphic Digital Circuits, In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop, Sopron, HU, UWH, 2005, s. 145-150, ISBN 9639364487
 Sekanina, L.: Evolucní design porází resení vytvorená kreativním návrhárem, In: Vesmír, roc. 84, c. 1, 2005, CZ, s. 44-46, ISSN 0042-4544
 Sekanina, L.: Evolutionary Design of Gate-Level Polymorphic Digital Circuits, In: Applications of Evolutionary Computation, Berlin, DE, Springer, 2005, s. 185-194, ISBN 978-3-540-25396-9
 Strnadel, J., Pecenka, T., Sekanina, L.: On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits, In: Proceedings of 5th Electronic Circuits and Systems Conference, Bratislava, SK, STUBA, 2005, s. 107-110
 Zebulum, R., S., Stoica, A., Keymeulen, D., Sekanina, L.: Evolvable Hardware System at Extreme Low Temperatures, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2005, s. 37-45, ISBN 978-3-540-28736-0
2004Friedl, S., Sekanina, L.: The First Circuits Evolved in a Physical Virtual Reconfigurable Device, In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Bratislava, SK, SAV, 2004, s. 35-42, ISBN 80-969117-9-1
 Kotásek, Z., Pecenka, T., Sekanina, L., Strnadel, J.: Evolutionary Design of Synthetic RTL Benchmark Circuits, In: Informal Digest of Papers, IEEE European Test Workshop 2004, Montpellier, FR, IEEE CS, 2004, s. 107-108, ISBN 000000000
 Kotásek, Z., Pecenka, T., Strnadel, J., Mika, D., Sekanina, L.: An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking, In: Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004, Kosice, SK, TU v Kosiciach, 2004, s. 229-234, ISBN 80-8073-150-0
 Ruzicka, R., Sekanina, L.: A Platform for Demonstration of Analogue and Digital Circuits Evolution, In: Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004, Kosice, SK, TU v Kosiciach, 2004, s. 158-163, ISBN 80-8073-150-0
 Sekanina, L., Drábek, V.: Theory and Applications of Evolvable Embedded Systems, In: Proc. of the 11th IEEE Int. Conference and Workshop on the Engineering of Computer-Based Systems, Los Alamitos, CA, US, ICSP, 2004, s. 186-193, ISBN 0-7695-2125-8
 Sekanina, L., Friedl, S.: An Evolvable Combinational Unit for FPGAs, In: Computing and Informatics, roc. 23, c. 5, 2004, Bratislava, SK, s. 461-486, ISSN 1335-9150
 Sekanina, L., Friedl, S.: On Routine Implementation of Virtual Evolvable Devices Using COMBO6, In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2004, s. 63-70, ISBN 0-7695-2145-2
 Sekanina, L.: Evolutionary Design Space Exploration for Median Circuits, In: Lecture Notes in Computer Science, roc. 2004, c. 3005, DE, s. 240-249, ISSN 0302-9743
 Sekanina, L.: Evolvable computing by means of evolvable components, In: Natural Computing, roc. 3, c. 3, 2004, Dordrecht, NL, s. 323-355, ISSN 15677818
 Sekanina, L.: Evolving Constructors for Infinitely Growing Sorting Networks and Medians, In: Lecture Notes in Computer Science, roc. 2004, c. 2932, DE, s. 314-323, ISSN 0302-9743
 Torresen, J., Bakke, J., W., Sekanina, L.: Efficient Image Filtering and Information Reduction in Reconfigurable Logic, In: Proc. of 2004 Norchip conference, Oslo, NO, ICSP, 2004, s. 63-66, ISBN 0-7803-8510-1
 Torresen, J., Bakke, J., W., Sekanina, L.: Efficient Recognition of Speed Limit Signs, In: Proc. of the 7th International IEEE Conference on Intelligent Transportation Systems, Los Alamos, US, ICSP, 2004, s. 652-656, ISBN 0-7803-8501-2
 Torresen, J., Bakke, J., W., Sekanina, L.: Recognizing Speed Limit Sign Numbers by Evolvable Hardware, In: Lecture Notes in Computer Science, roc. 2004, c. 3242, DE, s. 682-691, ISSN 0302-9743
 Vasícek, Z., Sekanina, L.: Evolucní návrh kombinacních obvodu, In: Elektrorevue - www.elektrorevue.cz, roc. 2004, c. 43, Brno, CZ, s. 1-6, ISSN 1213-1539

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