Prof. Ing. Lukáš Sekanina, Ph.D.

VAŠÍČEK Zdeněk and SEKANINA Lukáš. Hardware Accelerators for Cartesian Genetic Programming. In: Eleventh European Conference on Genetic Programming. Berlin: Springer Verlag, 2008, pp. 230-241. ISBN 978-3-540-78670-2.
Publication language:english
Original title:Hardware Accelerators for Cartesian Genetic Programming
Title (cs):Obvodové akcelerátory pro kartézské genetické programování
Proceedings:Eleventh European Conference on Genetic Programming
Conference:Eleventh European Conference on Genetic Programming
Series:LNCS 4971
Place:Berlin, DE
Publisher:Springer Verlag
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cartesian genetic programming, field programmable gate array, evolutionary design
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications.
Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.
   author = {Zden{\v{e}}k Va{\v{s}}{\'{i}}{\v{c}}ek and
	Luk{\'{a}}{\v{s}} Sekanina},
   title = {Hardware Accelerators for Cartesian Genetic
   pages = {230--241},
   booktitle = {Eleventh European Conference on Genetic Programming},
   series = {LNCS 4971},
   year = 2008,
   location = {Berlin, DE},
   publisher = {Springer Verlag},
   ISBN = {978-3-540-78670-2},
   language = {english},
   url = {}

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