Prof. Ing. Lukáš Sekanina, Ph.D.

STAREČEK Lukáš, SEKANINA Lukáš and KOTÁSEK Zdeněk. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008, pp. 255-258. ISBN 978-1-4244-2276-0.
Publication language:english
Original title:Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration
Title (cs):Redukce počtu testovacích vektorů pomocí rekonfigurace na úrovni hradel
Pages:255-258
Proceedings:Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Conference:IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Place:Bratislava, SK
Year:2008
ISBN:978-1-4244-2276-0
Publisher:IEEE Computer Society
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Keywords
digital circuit, test vector, reconfiguration
Annotation
In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.
BibTeX:
@INPROCEEDINGS{
   author = {Luk{\'{a}}{\v{s}} Stare{\v{c}}ek and Luk{\'{a}}{\v{s}}
	Sekanina and Zden{\v{e}}k Kot{\'{a}}sek},
   title = {Reduction of Test Vectors Volume by Means of Gate-Level
	Reconfiguration},
   pages = {255--258},
   booktitle = {Proc. of 2008 IEEE Design and Diagnostics of Electronic
	Circuits and Systems Workshop},
   year = {2008},
   location = {Bratislava, SK},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-2276-0},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8603}
}

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