Ing. Jaroslav Škarvada, Ph.D.

ŠKARVADA, J.. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Department of Computer Systems FIT BUT, 2009.
Publication language:czech
Original title:Optimalizace aplikace testu číslicových systémů pro nízký příkon
Title (en):Digital systems test application optimization for low power consumption
Pages:125
Place:Brno, CZ
Year:2009
Publisher:Department of Computer Systems FIT BUT
URL: [PDF]
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Keywords
Digital circuit, test vectors, scan registers, test optimization, power consumption reduction.
Abstract
The thesis deals with power consumption reduction of digital circuit during test application. Higher power consumption during the test application is problematic especially for VLSI circuits due to negative effects such as voltage drops on supply lines, electromigration resulting in connections cut, electromagnetic induction resulting in signals interference and overheating. In cases when the chip is not well designed for a such power consumption the test results can be affected. Designing the chip for the power consumption during the test application is expensive and non effective, because most of the time the chip will operate in normal functional mode and the design will be uselessly oversized. That is why the optimization methods for power consumption reduction during the test application were introduced. Generally the application of most of these methods prolongs the test such that the energy consumption is not reduced. But there also exist such specialized methods that allows not only the power reduction but also the energy consumption to be reduced. Such methods allow, for instance, cost reduction during the mass production of digital circuits due to energy savings at check out testing.
The thesis presents the analysis of sources of increased power consumption during the test application in comparison with normal functional mode of operation. Up to date methods for reduction of dynamic and static power during the test application are also described. Next the methodology for simultaneous reordering of test vectors and scan registers is proposed and described by algorithms. The methodology is primarily used for reduction of dynamic part of power for full scan based circuits, but can be used as well for combinatorial circuits only with the little drop in power reduction. The methodology also reduces the energy consumption during the test application. For the browsing of the large solution space of the task the genetic algorithm is used. For fitness calculation the power consumption value is used. The power consumption is evaluated by simulation of test application over the technological library. This approach allows to obtain more precise results in comparison with simple methods (e.g. methods based on computation of Hamming distance between test vectors). The method was implemented and applied on established benchmark sets. The results gained from experiments over these benchmarks and comparison with existing methods is also presented.
BibTeX:
@PHDTHESIS{
   author = {Jaroslav Škarvada},
   title = {Optimalizace aplikace testu číslicových systémů pro nízký
	příkon},
   pages = {125},
   year = {2009},
   location = {Brno, CZ},
   publisher = {Department of Computer Systems FIT BUT},
   language = {czech},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9089}
}

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