The tools from the RUZ package can be used for automatic transformation of digital circuit design written in structural VHDL to formal model that was developed at DCS FIT BUT. With these tools it is possible to perform transparent data paths (I-paths) search, testability analysis, scan chain design. Custom cell libraries can be also used.
Download: ruz-1.0.tar.gz
The RUZ package is now deprecated by the BEAST project.
Last modification: 2009-11-18