Ing. Azeddien M. Sllame, Ph.D.

Publications

2003SLLAME Azeddien M. A Pipeline Scheduling Algorithm for High-Level Synthesis. In: Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Elsevier Science, 2003, pp. 178-183. ISBN 0-08-044130-0.
2002SLLAME Azeddien M. Efficient Design Space Characterization Toward Realizing High-Performance Digital systems. In: Proceedings of Electronic Devices and Systems EDS'02 Conference. Brno: Brno University of Technology, 2002, pp. 144-149. ISBN 80-214-2180-0.
 SLLAME Azeddien M. and DRÁBEK Vladimír. A Design Space Exploration Scheme for High-Level Synthesis Systems. In: Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems. Ostrava, 2002, pp. 305-312. ISBN 80-85988-71-2.
 SLLAME Azeddien M. and DRÁBEK Vladimír. An Efficient List-Based Scheduling Algorithm for High-Level-Synthesis. In: EUROMICRO Symposium on Digital System Design (DSD2002): Architecture, Methods and Tools, IEEE Computer Society. Dortmund, Germany: IEEE Computer Society Press, 2002, pp. 316-323. ISBN 0-7695-1790-0.
 SLLAME Azeddien M. and SEKANINA Lukáš. An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis. In: Advances in Nature-Inspired Computation: The PPSN VII Workshops. Reading: PEDAL, Department of Computer Science, University of Reading, 2002, pp. 45-46. ISBN 0-9543481-0-9.
 SLLAME Azeddien M. and SEKANINA Lukáš. An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis. In: Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002, pp. 87-92. ISBN 80-214-2135-5.
2001SLLAME Azeddien M. Modeling and Prototyping of Signal and Image Processing Algorithms in VHDL. In: 10th International Conference on System Modelling Control SMC'01. Lodz, 2001, pp. 201-205. ISBN 83-7283-026-6.
 SLLAME Azeddien M. and DRÁBEK Vladimír. Specification and Synthesis of Reusable Modules in VHDL. In: Proceedings of fourth International Wokshop on IEEE Design and Diagnostics of Electronic Circuits and Systems IEEE DDCSE01. Gyor, Hungary: SZIF-UNIVERSITAS Ltd., Hungary, 2001, pp. 137-140. ISBN 963-7175-16-4.
2000SEKANINA Lukáš and SLLAME Azeddien M. Toward Uniform Approach to Design of Evolvable Hardware Based Systems. Lecture Notes in Computer Science. 2000, vol. 2000, no. 1896, pp. 814-817. ISSN 0302-9743.
 SLLAME Azeddien M. Design Exploration Based Reusability Method, In: Student Conference STC2000, FEI VUT Brno. In: Student Conference STC2000 FEI VUT Brno. Brno: Akademické nakladatelství CERM, 2000, pp. 240-242. ISBN 80-7204-155-X.
 SLLAME Azeddien M. and DRÁBEK Vladimír. Design of Graphical Hardware. In: MOSIS2000 34th Spring International Conference Modeling and Simulation of Systems. Roznov pod Radhostem, 2000, pp. 51-55. ISBN 80-85988-44-5.
 SLLAME Azeddien M. and SEKANINA Lukáš. Simulation and Modeling of Evolvable Hardware Based Systems. In: MS2000 International Conference on Modeling and Simulation. Las Palmas de Gran Canaria: unknown, 2000, pp. 485-492. ISBN 84-95286-59-9.
1999SLLAME Azeddien M. Algorithmic designs using behavioral compiler, In: Sbornik praci studentu a doktorandu FEI VUT Brno. In: Sbornik praci studentu a doktorandu FEI VUT Brno. Brno: Akademické nakladatelství CERM, 1999, pp. 107-108. ISBN 80-214-1155-4.
 SLLAME Azeddien M. Component reuse and recursivness in VHDL modeling: a paractical experiance. In: Roznov pod Radhostem: unknown, 1999, pp. 51-58. ISBN 80-85988-33-X.
 SLLAME Azeddien M. Designing on Algorithmic Level Using Behavioral Compiler, In:EDS'99, Brno. In: Electronic Devices and Systems 1999 - Proceedings. Brno: Akademické nakladatelství CERM, 1999, pp. 121-124. ISBN 80-214-1466-9.
 SLLAME Azeddien M. Usefulness of Component Reuse in Synthesising VHDL Designs. In: IEEE International Workshop on Logic Synthesis, IWLS99. Granlibakken Resort, Lake Tahoe, California: unknown, 1999, p. 1.

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