Modeling and Prototyping of Signal and Image Processing Algorithms in VHDL

Modeling, prototyping, VHDL.

Signal and image processing algorithms are well known as highly computation-intensive ones. In this paper we will demonstrate that these highly computational demanding algorithms can be efficiently simulated, modeled, prototyped in VHDL, and then realized on hardware. We start the initial specification by specifying the given algorithm in the behavioral level (i.e. algorithmic description), then the design is verified using test bench. High-level synthesis tools is used to make design space exploration and to produce RTL description for final prototyping in VHDL, and realization of the specified algorithm using FPGA technology.