In main.cc, it is demonstrated
SYNTAX: ./taste -iTA <file> [option(s)] options: -license_read use only if you have already read license conditions -h display (this) help information -scan turn scan mode ON -design turn design mode ON -cir <name> set name of circuit and turns circuit mode ON -i <file> specify file containing circuit/design data -seqest specify way of sequential length estimation -propen specify way a propagation penalty is evaluated -ta run testability analysis of given circuit -o <format(s)> output format(s) for storing testability analysis results, where 'formats' can be one or comma-separated combination of html, tex, txt -T <file(s)> specify explicit library/ies of available module-types (otherwise, implicit library taste.templates taken) -freg <file> specify explicit file with circuit/design register list (otherwise, implicit *.reg will be taken) -fscan <file> specify explicit file with circuit/design scan notation (otherwise, implicit *.scan will be taken)
Let us take some examples of utilizing the interface in order to perform desired actions over a design.
./taste
command is run, a user is informed about necessity of reading all license conditions before using TASTE.
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TASTE (Testability Analysis SuiTE) v1.00
Copyright (c) 2008 Josef Strnadel
Developped at Brno University of Technology, Faculty of Information Technology
This software comes with ABSOLUTELY NO WARRANTY; for details use `-show w'.
You are welcome to use, modify and/or redistribute the software under certain conditions; use `-show c' for details.
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PLEASE, READ ALL LICENSE CONDITIONS and documentation BEFORE USING TASTE!
PRESS ANY KEY TO CONTINUE...
Only if the conditions are read by the user, user is allowed to use license_read flag after taste command:
./taste -license_read
At least input file (containing a netlist) should be specified by means of parameter -i (in the example's case, the file is stored in examples/ directory):
./taste -license_read -i examples/nl
After action is finished, text
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TASTE (Testability Analysis SuiTE) v1.00
Copyright (c) 2008 Josef Strnadel
Developped at Brno University of Technology, Faculty of Information Technology
This software comes with ABSOLUTELY NO WARRANTY; for details use `-show w'.
You are welcome to use, modify and/or redistribute the software under certain conditions; use `-show c' for details.
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Processing design named 'top_level'...
Loading templates from 'taste.templates'... [OK]
Loading netlist from 'examples/nl' - circuit 'NestedLoops' loaded... [OK]
TASTE ended with 0 error(s) and 0 warning(s).
should be present in your command-line.
If an action is to be performed over a single circuit within the design (actually, there is no other variant to this because design is supposed to consist of single circuit only in actual version of TASTE), name of the circuit should be specified. This could be done by means of parameter -cir . For example, above-mentioned netlist stored in examples/nl contains circuit named NestedLoops . So, the command could have following form:
./taste -license_read -i examples/nl -cir NestedLoops
./taste -license_read -i examples/nl -cir NestedLoops -ta
After action is finished, text
...
Testability analysis of circuit 'NestedLoops' done.
TASTE ended with 0 error(s) and 0 warning(s).
should be present in your command-line.
./taste -license_read -i examples/nl -cir NestedLoops -ta -o htm ... Saving testability information of circuit 'NestedLoops' into file 'examples/nl_TA.html' TASTE ended with 0 error(s) and 0 warning(s).
... LaTEX ...
./taste -license_read -i examples/nl -cir NestedLoops -ta -o tex ... Saving testability information of circuit 'NestedLoops' into file 'examples/nl_TA.tex' TASTE ended with 0 error(s) and 0 warning(s).
... or plain-text format:
./taste -license_read -i examples/nl -cir NestedLoops -ta -o txt ... Saving testability information of circuit 'NestedLoops' into file 'examples/nl_TA.txt' TASTE ended with 0 error(s) and 0 warning(s).
Of course, any combination of the formats can be selected, e.g.:
./taste -license_read -i examples/nl -cir NestedLoops -ta -o txt tex ./taste -license_read -i examples/nl -cir NestedLoops -ta -o txt htm ./taste -license_read -i examples/nl -cir NestedLoops -ta -o txt tex htm
The first file (named *.reg) contains list of names of registers (separated by space character) present in circuit structure. As an example of such a file, see containts of examples/nl.reg file:
R1 R2 R3
The second file (named *.scan) contains information about scan chains to be implemented into the structure. As an example of such a file, see containts of self-explaining examples/nl.scan file:
--- below, following scan-related config is stored:
--- 1st line: scan-register type used for reg->scan_reg. modification
--- 2nd line: register scan input, scan output, scan mode, clock port names
--- 3rd line: PI/PO scan input, scan output, scan mode, clock port names
SREG_<n>
scan_in scan_out scan_mode
s_in s_out mode
--- below, place scan chain per a line; registers within the chain are to be separated by a space character
R3 R2
R1
After both *.reg and *.scan files are present, scan can be implemented by means of '-scan' command-line switch:
./taste -license_read -i examples/nl -cir NestedLoops -scan ... List of registers will be taken from implicit 'examples/nl.reg' file. Data related to scan will be taken from implicit 'examples/nl.scan' file. TASTE ended with 0 error(s) and 0 warning(s).
Of course, testability analysis can be performed over such a design by means of -ta switch, e.g.
./taste -license_read -i examples/nl -cir NestedLoops -scan -ta
and testability analysis results saved by means of -o option, e.g.
./taste -license_read -i examples/nl -cir NestedLoops -scan -ta -o txt
./taste -license_read -i examples/nl -cir NestedLoops -scan -ta -o txt -seqest precise
./taste -license_read -i examples/nl -cir NestedLoops -scan -ta -o txt -propen linear
1.5.6