(chronological list of some materials utilizable for deeper study of related concepts)
- Strnadel, J.: TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path, 2008, p. 8
- Pecenka, T., Strnadel, J., Kotasek, Z., Sekanina, L.: Testability Estimation Based on Controllability and Observability Parameters, In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06), Cavtat, HR, IEEE CS, 2006, p. 504-514, ISBN 0-7695-2609-8
- Strnadel, J.: Testability Analysis and Improvements of Register-Transfer Level Digital Circuits, In: Computing and Informatics, Vol. 25, No. 5, 2006, Bratislava, SK, p. 441-464, ISSN 1335-9150
- Pecenka, T., Kotasek, Z., Sekanina, L., Strnadel, J.: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties, In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2005, p. 51-58, ISBN 0-7695-2399-4
- Y. Makris, A. Orailoglu, Property-Based Testability Analysis for Hierarchical RTL Designs, Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS), pp. 1089-1092, 1999
- Abadir, M.S., Breuer, M. A.: A Knowledge-Based System for Designing Testable VLSI Chips, IEEE Design and Test of Computers, Vol. 2, No. 4, 1985, pp. 56-68
All author's publications can be found at
http://www.fit.vutbr.cz/~strnadel/pubs.php.en . If you would like to read publication(s) whose text is not accessible through the above-mentioned link or your library, please contact me at
strnadel@fit.vutbr.cz
