Project Details

Optimalizační postupy v diagnostice číslicových systémů

Project Period: 1. 1. 2005 - 31. 12. 2007

Project Type: grant

Code: GP102/05/P193

Agency: Czech Science Foundation

Program:

English title
Optimizing Methods in Digital Systems Diagnosis
Type
grant
Keywords

optimizing methods; trade-off; diagnosis; design constraints; digital system

Abstract

In both digital circuit design area and diagnosis area a feasible trade-off among various constraints is to be investigated for the purposes of a successful solving of partial problems. The quality of the trade-off has a real impact on competition abilities of a result product. Usually, simple trade-offs can be resolved by a human, while the complex ones by an automated process. In this project, selected optimization problems from the area of digital circuit diagnosis will be dealt and solved; they will be formally described and utilized to speed-up the optimization process by injecting a very deep knowledge about the problem to the process (e.g., the speed-up can be done by a proper reduction of the problem search space). Further goals of the project are: algorithmization of the proposed methods, their implementation and verification on a set of digital systems, presentation and publication of gained results on conferences and workshops from digital circuit design and diagnosis area.

Team members
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT) , research leader
Publications

2008

  • STRNADEL Josef, PEČENKA Tomáš and KOTÁSEK Zdeněk. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, vol. 27, no. 6, 2008, pp. 913-930. ISSN 1335-9150. Detail

2007

  • STRNADEL Josef. Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade-Offs Related to Digital Circuit Diagnosis. In: Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2007, pp. 333-338. ISBN 978-80-214-3470-7. Detail
  • STRNADEL Josef. On Encoding and Utilization of Diagnostic Information Extracted from Design-Data for Testability Analysis Purposes. In: Proceedings of the 6th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2007, pp. 171-176. ISBN 978-80-227-2697-9. Detail

2006

  • STRNADEL Josef and DHALI Arghya. Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, pp. 360-367. ISBN 0-7695-2546-6. Detail
  • STRNADEL Josef. On Distribution of Testability Values in Scan-Layout State-Space. In: Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006, pp. 308-313. ISBN 80-8073-598-0. Detail
  • STRNADEL Josef. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006, pp. 161-162. ISBN 1-4244-0184-4. Detail
  • KOTÁSEK Zdeněk and STRNADEL Josef. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, pp. 497-498. ISBN 0-7695-2546-6. Detail
  • STRNADEL Josef. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, vol. 25, no. 5, 2006, pp. 441-464. ISSN 1335-9150. Detail

2005

  • STRNADEL Josef and KOTÁSEK Zdeněk. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In: Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, pp. 420-427. ISBN 0-7695-2433-8. Detail
  • STRNADEL Josef, PEČENKA Tomáš and SEKANINA Lukáš. On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits. In: Proceedings of 5th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2005, pp. 107-110. Detail
  • KOTÁSEK Zdeněk and STRNADEL Josef et al. Testing Tools for Training and Education. In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005, pp. 671-676. ISBN 83-919289-9-3. Detail
  • STRNADEL Josef. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. In: Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 190-193. ISBN 963-9364-48-7. Detail
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