Ing. Josef Strnadel, Ph.D.

2013STRNADEL Josef. Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. In: Architecture of Computing Systems - ARCS 2013. Berlin: Springer Verlag, 2013, pp. 98-109. ISBN 978-3-642-36423-5. ISSN 0302-9743.
 STRNADEL Josef. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013, pp. 24-29. ISBN 978-1-4673-6133-0.
 STRNADEL Josef. Plánování úloh v systémech RT - IV: víceprocesorové prostředí. Automa. 2013, vol. 19, no. 1, pp. 44-46. ISSN 1210-9592.
 STRNADEL Josef. Plánování úloh v systémech RT - V: zvyšování provozuschopnosti systémů. Automa. 2013, vol. 19, no. 2, pp. 46-49. ISSN 1210-9592.
2012STRNADEL Josef and RAJNOHA Peter. Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study. Acta Electrotechnica et Informatica. 2012, vol. 12, no. 4, pp. 17-29. ISSN 1335-8243.
 STRNADEL Josef and SLIMAŘÍK František. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. In: Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012, pp. 272-279. ISBN 978-0-7695-4798-5.
 STRNADEL Josef. Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems. In: Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallin: IEEE Computer Society, 2012, pp. 121-126. ISBN 978-1-4673-1188-5.
 STRNADEL Josef. Plánování úloh v systémech RT - I: závislé úlohy. Automa. 2012, vol. 18, no. 10, pp. 42-45. ISSN 1210-9592.
 STRNADEL Josef. Plánování úloh v systémech RT - II: neperiodické úlohy. Automa. 2012, vol. 18, no. 11, pp. 44-46. ISSN 1210-9592.
 STRNADEL Josef. Plánování úloh v systémech RT - III: přetížení systému. Automa. 2012, vol. 18, no. 12, pp. 44-47. ISSN 1210-9592.
2011RUMPLÍK Michal and STRNADEL Josef. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011, pp. 367-374. ISBN 978-0-7695-4494-6.
 STRNADEL Josef. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011, pp. 21-22. ISBN 978-3-902457-30-1.
 STRNADEL Josef. Návrh časově kritických systémů III: priorita úloh. Automa. 2011, vol. 2011, no. 2, pp. 50-52. ISSN 1210-9592.
 STRNADEL Josef. Návrh časově kritických systémů IV: realizace prostředky RTOS. Automa. 2011, vol. 2011, no. 4, pp. 58-60. ISSN 1210-9592.
 STRNADEL Josef. Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems. In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium. Vienna: TU Vienna, 2011, pp. 29-32.
2010KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 364-369. ISBN 978-1-4244-6610-8.
 KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010, pp. 644-651. ISBN 978-0-7695-4171-6.
 STRNADEL Josef. Návrh časově kritických systémů I: specifikace a verifikace. Automa. 2010, vol. 2010, no. 10, pp. 42-44. ISSN 1210-9592.
 STRNADEL Josef. Návrh časově kritických systémů II: úlohy reálného času. Automa. 2010, vol. 2010, no. 12, pp. 18-19. ISSN 1210-9592.
 STRNADEL Josef. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. In: Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Tomas Bata University in Zlín, 2010, pp. 99-104. ISBN 978-80-7318-940-2.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Faculty of Information Technology BUT, 2010. ISBN 978-80-214-4209-2.
 ŠKARVADA Jaroslav, KOTÁSEK Zdeněk and STRNADEL Josef. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2010, pp. 181-192. ISBN 978-3-642-15322-8. ISSN 0302-9743.
2009STRNADEL Josef and RŮŽIČKA Richard. Testability Analysis Driven Data Path Modification And Controller Synthesis. In: Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2009, pp. 363-368. ISBN 978-80-214-3933-7.
 STRNADEL Josef. Univerzitní týmy soutěží na autodráze. Události (VUT News). 2009, vol. 2009, no. 4. ISSN 1211-4421.
 STRNADEL Josef. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. In: Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Tomas Bata University in Zlín, 2009, pp. 19-24. ISBN 978-80-7318-840-5.
2008STRNADEL Josef, PEČENKA Tomáš and KOTÁSEK Zdeněk. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics. Bratislava: Slovak Academic Press, 2008, vol. 27, no. 6, pp. 913-930. ISSN 1335-9150.
 STRNADEL Josef. Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů. Brno: Faculty of Information Technology BUT, 2008. ISBN 978-80-214-3599-5.
 STRNADEL Josef. TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008, pp. 865-872. ISBN 978-0-7695-3277-6.
 STRNADEL Josef. Testability Enhancement of Multilevel Designs Guided by Testability Analysis Method. In: Proceedings of Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2008, pp. 367-372. ISBN 978-80-214-3717-3.
2007RŮŽIČKA Richard and STRNADEL Josef. Test Controller Synthesis Constrained by Circuit Testability Analysis. In: Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007, pp. 626-633. ISBN 0-7695-2978-X.
 STRNADEL Josef. Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade-Offs Related to Digital Circuit Diagnosis. In: Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2007, pp. 333-338. ISBN 978-80-214-3470-7.
 STRNADEL Josef. On Encoding and Utilization of Diagnostic Information Extracted from Design-Data for Testability Analysis Purposes. In: Proceedings of the 6th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2007, pp. 171-176. ISBN 978-80-227-2697-9.
2006KOTÁSEK Zdeněk and STRNADEL Josef. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, pp. 497-498. ISBN 0-7695-2546-6.
 PEČENKA Tomáš, STRNADEL Josef, KOTÁSEK Zdeněk and SEKANINA Lukáš. Testability Estimation Based on Controllability and Observability Parameters. In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). Cavtat: IEEE Computer Society, 2006, pp. 504-514. ISBN 0-7695-2609-8.
 STRNADEL Josef and DHALI Arghya. Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006, pp. 360-367. ISBN 0-7695-2546-6.
 STRNADEL Josef. On Distribution of Testability Values in Scan-Layout State-Space. In: Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006, pp. 308-313. ISBN 80-8073-598-0.
 STRNADEL Josef. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006, pp. 161-162. ISBN 1-4244-0184-4.
 STRNADEL Josef. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics. Bratislava: Slovak Academic Press, 2006, vol. 25, no. 5, pp. 441-464. ISSN 1335-9150.

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