Ing. Josef Strnadel, Ph.D.

2013Strnadel, J.: Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates, In: Architecture of Computing Systems - ARCS 2013, Berlin, DE, Springer, 2013, p. 98-109, ISBN 978-3-642-36423-5
 Strnadel, J.: On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems, In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electrical Circuits and Systems, Brno, CZ, IEEE CS, 2013, p. 24-29, ISBN 978-1-4673-6136-1
 Strnadel, J.: Plánování úloh v systémech RT - IV: víceprocesorové prostředí, In: Automa, Vol. 19, No. 1, 2013, CZ, p. 44-46, ISSN 1210-9592
 Strnadel, J.: Plánování úloh v systémech RT - V: zvyšování provozuschopnosti systémů, In: Automa, Vol. 19, No. 2, 2013, CZ, p. 46-49, ISSN 1210-9592
2012Strnadel, J., Rajnoha, P.: Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study, In: Acta Electrotechnica et Informatica, Vol. 12, No. 4, 2012, SK, p. 17-29, ISSN 1335-8243
 Strnadel, J., Slimařík, F.: On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels, In: Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Pistacaway, US, IEEE CS, 2012, p. 272-279, ISBN 978-0-7695-4798-5
 Strnadel, J.: Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems, In: Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallin, EE, IEEE CS, 2012, p. 121-126, ISBN 978-1-4673-1188-5
 Strnadel, J.: Plánování úloh v systémech RT - III: přetížení systému, In: Automa, Vol. 18, No. 12, 2012, CZ, p. 44-47, ISSN 1210-9592
 Strnadel, J.: Plánování úloh v systémech RT - II: neperiodické úlohy, In: Automa, Vol. 18, No. 11, 2012, CZ, p. 44-46, ISSN 1210-9592
 Strnadel, J.: Plánování úloh v systémech RT - I: závislé úlohy, In: Automa, Vol. 18, No. 10, 2012, CZ, p. 42-45, ISSN 1210-9592
2011Rumplík, M., Strnadel, J.: On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits, In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011, Oulu, FI, IEEE CS, 2011, p. 367-374, ISBN 978-0-7695-4494-6
 Strnadel, J.: Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads, In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design, Oulu, FI, JKUL, 2011, p. 21-22, ISBN 978-3-902457-30-1
 Strnadel, J.: Návrh časově kritických systémů III: priorita úloh, In: Automa, Vol. 2011, No. 2, CZ, p. 50-52, ISSN 1210-9592
 Strnadel, J.: Návrh časově kritických systémů IV: realizace prostředky RTOS, In: Automa, Vol. 2011, No. 4, CZ, p. 58-60, ISSN 1210-9592
 Strnadel, J.: Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems, In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium, Vienna, AT, TUV, 2011, p. 29-32
2010Kotásek, Z., Škarvada, J., Strnadel, J.: Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences, In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, p. 364-369, ISBN 978-1-4244-6610-8
 Kotásek, Z., Škarvada, J., Strnadel, J.: The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption, In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools, Los Alamitos, US, IEEE CS, 2010, p. 644-651, ISBN 978-0-7695-4171-6
 Strnadel, J.: Návrh časově kritických systémů II: úlohy reálného času, In: Automa, Vol. 2010, No. 12, CZ, p. 18-19, ISSN 1210-9592
 Strnadel, J.: Návrh časově kritických systémů I: specifikace a verifikace, In: Automa, Vol. 2010, No. 10, CZ, p. 42-44, ISSN 1210-9592
 Strnadel, J.: Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel, In: Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010, Zlín, CZ, UTB ve Zlíně, 2010, p. 99-104, ISBN 978-80-7318-940-2
 Škarvada, J., Kotásek, Z., Strnadel, J.: Optimalizace aplikace testu číslicových systémů pro nízký příkon, Brno, CZ, FIT VUT, 2010, p. 142, ISBN 978-80-214-4209-2
 Škarvada, J., Kotásek, Z., Strnadel, J.: The Use of Genetic Algorithm to Reduce Power Consumption during Test Application, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2010, p. 181-192, ISBN 978-3-642-15322-8
2009Strnadel, J., Růžička, R.: Testability Analysis Driven Data Path Modification And Controller Synthesis, In: Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference, Brno, CZ, VUT v Brně, 2009, p. 363-368, ISBN 978-80-214-3933-7
 Strnadel, J.: Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems, In: Proceedings of 32th International Conference TD - DIAGON 2009, Zlín, CZ, UTB ve Zlíně, 2009, p. 19-24, ISBN 978-80-7318-840-5
 Strnadel, J.: Univerzitní týmy soutěží na autodráze, In: Události (VUT News), Vol. 2009, No. 4, CZ, p. 26-26, ISSN 1211-4421
2008Strnadel, J., Pečenka, T., Kotásek, Z.: Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits, In: Computing and Informatics, Vol. 27, No. 6, 2008, Bratislava, SK, p. 913-930, ISSN 1335-9150
 Strnadel, J.: Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů, Brno, CZ, FIT VUT, 2008, p. 187, ISBN 978-80-214-3599-5
 Strnadel, J.: TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path, In: Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools, Los Alamitos, US, IEEE CS, 2008, p. 865-872, ISBN 978-0-7695-3277-6
 Strnadel, J.: Testability Enhancement of Multilevel Designs Guided by Testability Analysis Method, In: Proceedings of Electronic Devices and Systems IMAPS CS International Conference, Brno, CZ, VUT v Brně, 2008, p. 367-372, ISBN 978-80-214-3717-3
2007Růžička, R., Strnadel, J.: Test Controller Synthesis Constrained by Circuit Testability Analysis, In: Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Los Alamitos, US, ICSP, 2007, p. 626-633, ISBN 0-7695-2978-X
 Strnadel, J.: Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade-Offs Related to Digital Circuit Diagnosis, In: Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference, Brno, CZ, VUT v Brně, 2007, p. 333-338, ISBN 978-80-214-3470-7
 Strnadel, J.: On Encoding and Utilization of Diagnostic Information Extracted from Design-Data for Testability Analysis Purposes, In: Proceedings of the 6th Electronic Circuits and Systems Conference, Bratislava, SK, STUBA, 2007, p. 171-176, ISBN 978-80-227-2697-9
2006Kotásek, Z., Strnadel, J.: SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System, In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS), Los Alamitos, CA, US, IEEE CS, 2006, p. 497-498, ISBN 0-7695-2546-6
 Pečenka, T., Strnadel, J., Kotásek, Z., Sekanina, L.: Testability Estimation Based on Controllability and Observability Parameters, In: Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06), Cavtat, HR, IEEE CS, 2006, p. 504-514, ISBN 0-7695-2609-8
 Strnadel, J., Dhali, A.: Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules, In: Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS), Los Alamitos, CA, US, IEEE CS, 2006, p. 360-367, ISBN 0-7695-2546-6
 Strnadel, J.: On Distribution of Testability Values in Scan-Layout State-Space, In: Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics, Košice, SK, TU v Košiciach, 2006, p. 308-313, ISBN 80-8073-598-0
 Strnadel, J.: Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space, In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Prague, CZ, VCVUT, 2006, p. 161-162, ISBN 1-4244-0184-4
 Strnadel, J.: Testability Analysis and Improvements of Register-Transfer Level Digital Circuits, In: Computing and Informatics, Vol. 25, No. 5, 2006, Bratislava, SK, p. 441-464, ISSN 1335-9150
2005Kotásek, Z., Strnadel, J. et al: Testing Tools for Training and Education, In: Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems, Krakow, PL, DMCS-TUL, 2005, p. 671-676, ISBN 83-919289-9-3
 Kotásek, Z., Strnadel, J., Pečenka, T.: Methodology of Selecting Scan-Based Testability Improving Technique, In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop, Sopron, HU, UWH, 2005, p. 186-189, ISBN 963-9364-48-7
 Pečenka, T., Kotásek, Z., Sekanina, L., Strnadel, J.: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties, In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2005, p. 51-58, ISBN 0-7695-2399-4
 Strnadel, J., Kotásek, Z.: Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies, In: Proceedings of 8th Euromicro Conference on Digital System Design, Los Alamitos, US, IEEE CS, 2005, p. 420-427, ISBN 0-7695-2433-8
 Strnadel, J., Pečenka, T., Sekanina, L.: On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits, In: Proceedings of 5th Electronic Circuits and Systems Conference, Bratislava, SK, STUBA, 2005, p. 107-110
 Strnadel, J.: VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements, In: Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop, Sopron, HU, UWH, 2005, p. 190-193, ISBN 963-9364-48-7

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