Doc. Ing. Zdeněk Vašíček, Ph.D.

Advanced parallel and embedded computer systems

Czech title:Pokročilé paralelní a vestavěné počítačové systémy
Reseach leader:Sekanina Lukáš
Team leaders:Bartoš Václav, Bidlo Michal, Budiský Jakub, Crha Adam, Čekan Ondřej, Čudová Marta, Dobai Roland, Fučík Otto, Fukač Tomáš, Grochol David, Hrbáček Radek, Husa Jakub, Hyrš Martin, Jaroš Jiří, Kekely Lukáš, Kekely Michal, Kešner Filip, Kidoň Marek, Kořenek Jan, Krčma Martin, Krobot Pavel, Kučera Jan, Lojda Jakub, Martínek Tomáš, Matoušek Denis, Matoušek Jiří, Mrázek Vojtěch, Nevoral Jan, Nikl Vojtěch, Pánek Richard, Podivínský Jakub, Riša Michal, Růžička Richard, Strnadel Josef, Szurman Karel, Šimek Václav, Vašíček Zdeněk, Vaverka Filip, Viktorin Jan, Vrána Roman, Wiglasz Michal, Wrona Jan, Zachariášová Marcela
Agency:Brno University of Technology
Code:FIT-S-17-3994
Start:2017-03-01
End:2019-12-31
Keywords:embedded system, field programmable gate array, parallel system, optimization
Annotation:
Searching and validating new algorithms and computing platforms that can be used to design, optimize and implement modern computer systems. We primarily will deal with systems that are based on reconfigurable or multiprocessor architectures, have built-in systems, a higher level of reliability, and optimization based on a variety of criteria. Emphasis is placed on intensifying the PhD student's share of results and the presentation of results at international level.

Publications

2018CRHA Adam, ŠIMEK Václav and RŮŽIČKA Richard. Towards novel format for representation of polymorphic circuits. In: 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018, pp. 1-2. ISBN 978-1-5386-5290-9.
 FIŠER Petr and ŠIMEK Václav. Optimum Polymorphic Circuits Synthesis Method. In: 13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Taormina: IEEE Circuits and Systems Society, 2018, pp. 1-6. ISBN 978-1-5386-5290-9.
 JAROŠ Marta. Scientific Workflows Management. In: Počítačové architektúry & diagnostika PAD 2018. Plzeň: University of West Bohemia in Pilsen, 2018, pp. 25-28. ISBN 978-80-261-0814-6.
 LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 5-8. ISBN 978-80-261-0814-6.
 LOJDA Jakub and KOTÁSEK Zdeněk. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018, pp. 31-32. ISBN 978-80-01-06456-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 80-86. ISBN 978-1-5386-5709-6.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 244-251. ISBN 978-1-5386-7376-8.
 MATOUŠEK Denis, KUBIŠ Juraj, MATOUŠEK Jiří and KOŘENEK Jan. Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, pp. 104-110. ISBN 978-1-4503-5902-3.
 MATOUŠEK Denis, MATOUŠEK Jiří and KOŘENEK Jan. High-speed Regular Expression Matching with Pipelined Memory-based Automata. Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines. Boulder, CO: IEEE Computer Society, 2018. ISBN 978-1-5386-5522-1.
 MRÁZEK Vojtěch and VAŠÍČEK Zdeněk. Evolutionary Design of Large Approximate Adders Optimized for Various Error Criteria. In: Proceedings of the Genetic and Evolutionary Computation Conference Companion (GECCO '18). Kyoto: Association for Computing Machinery, 2018, pp. 294-295. ISBN 978-1-4503-5764-7.
 NEVORAL Jan, RŮŽIČKA Richard and ŠIMEK Václav. CMOS Gates with Second Function. In: 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Hong Kong: IEEE Computer Society, 2018, pp. 82-87. ISBN 978-1-5386-7099-6.
 NEVORAL Jan, RŮŽIČKA Richard and ŠIMEK Václav. From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs. In: 2018 21st Euromicro Conference on Digital System Design. Praha: Institute of Electrical and Electronics Engineers, 2018, pp. 657-664. ISBN 978-1-5386-7376-8.
 NIKL Vojtěch, ŘÍHA Lubomír, VYSOCKÝ Ondřej and ZAPLETAL Jan. Optimal Hardware Parameters Prediction for Best Energy-to-Solution of Sparse Matrix Operations Using Machine Learning Techniques. In: INFOCOMP 2018. Barcelona: International Academy, Research, and Industry Association, 2018, pp. 43-48. ISBN 978-1-61208-655-2.
 PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018, pp. 33-34. ISBN 978-80-01-06456-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 63-69. ISBN 978-1-5386-5709-6.
 PODIVÍNSKÝ Jakub, LOJDA Jakub and KOTÁSEK Zdeněk. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. In: INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť, 2018, pp. 9-12.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej and KOTÁSEK Zdeněk. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 229-236. ISBN 978-1-5386-7376-8.
 PÁNEK Richard, LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Communications Society, 2018, pp. 129-134. ISBN 978-1-5386-5709-6.
 PÁNEK Richard. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. In: Počítačové architektury & diagnostika 2018. Stachy: University of West Bohemia in Pilsen, 2018, pp. 21-24. ISBN 978-80-261-0814-6.
 STRNADEL Josef. Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Design & Test. Pistacaway: IEEE Circuits and Systems Society, 2018, vol. 35, no. 2, pp. 57-63. ISSN 2168-2356.
 TREFZER Martin A. and SEKANINA Lukáš. Guest Editorial: Bio-inspired Hardware and Evolvable Systems. IET Computers & Digital Techniques. Stevenage: The Institution of Engineering and Technology, 2018, vol. 12, no. 4. ISSN 1751-8601.
 ČEKAN Ondřej, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Program Generation Through a Probabilistic Constrained Grammar. In: Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018, pp. 214-220. ISBN 978-1-5386-7376-8.
2017KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5.
 KEŠNER Filip, SEKANINA Lukáš and BRÁZDIL Milan. Modular Framework for Detection of Inter-ictal Spikes in iEEG. In: The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17). Los Alamos: Institute of Electrical and Electronics Engineers, 2017, pp. 418-421. ISBN 978-1-5090-2809-2.
 KIDOŇ Marek and DOBAI Roland. Evolutionary design of hash functions for IP address hashing using genetic programming. In: 2017 IEEE Congress on Evolutionary Computation (CEC). San Sebastian: Institute of Electrical and Electronics Engineers, 2017, pp. 1720-1727. ISBN 978-1-5090-4601-0.
 KOŘENEK Jan and KEKELY Michal. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1.
 KRČMA Martin and KOTÁSEK Zdeněk. Approximation accuracy of different FPNN types. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
 KRČMA Martin, LOJDA Jakub and KOTÁSEK Zdeněk. Triple Modular Redundancy Used in Field Programmable Neural Networks. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-3298-7.
 LOJDA Jakub and KOTÁSEK Zdeněk. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 79-80. ISBN 978-80-01-06178-7.
 LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 59-62. ISBN 978-80-972784-0-3.
 LOJDA Jakub, PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 359-364. ISBN 978-1-5386-3298-7.
 LOJDA Jakub, PODIVÍNSKÝ Jakub, KOTÁSEK Zdeněk and KRČMA Martin. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In: Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017, pp. 273-278. ISBN 978-1-5386-3298-7.
 PODIVÍNSKÝ Jakub and KOTÁSEK Zdeněk. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. In: Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017, pp. 81-82. ISBN 978-80-01-06178-7.
 PODIVÍNSKÝ Jakub, LOJDA Jakub, ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Reliability Analysis and Improvement of FPGA-based Robot Controller. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017, pp. 337-344. ISBN 978-1-5386-2146-2.
 PODIVÍNSKÝ Jakub, ČEKAN Ondřej, LOJDA Jakub, ZACHARIÁŠOVÁ Marcela, KRČMA Martin and KOTÁSEK Zdeněk. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2017, vol. 52, no. 5, pp. 145-159. ISSN 0141-9331.
 PÁNEK Richard. Systémy odolné proti poruchám - metodika návrhu řadiče rekonfigurace. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 24-27. ISBN 978-80-972784-0-3.
 SHAFIQUE Muhammad, HAFIZ Rehan, JAVED Muhammad Usama, ABBAS Sarmad, SEKANINA Lukáš, VAŠÍČEK Zdeněk and MRÁZEK Vojtěch. Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. In: 2017 IEEE Computer Society Annual Symposium on VLSI. Los Alamitos: IEEE Computer Society Press, 2017, pp. 627-632. ISBN 978-1-5090-6762-6.
 STRNADEL Josef. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In: Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017, pp. 352-355. ISBN 978-1-5386-2146-2.
 SZURMAN Karel and KOTÁSEK Zdeněk. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. In: Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 51-54. ISBN 978-80-972784-0-3.
 VYSOCKÝ Ondřej, BESEDA Martin, ŘÍHA Lubomír, ZAPLETAL Jan, NIKL Vojtěch, LYSAGHT Michael and KANNAN Venkatesh. Evaluation of the HPC Applications Dynamic Behavior in Terms of Energy Consumption. In: PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, GRID AND CLOUD COMPUTING FOR ENGINEERING. Stirlingshire: Civil-Comp Press, 2017, pp. 30-49. ISBN 978-1-905088-66-9.
 WIGLASZ Michal and SEKANINA Lukáš. Evolutionary Approximation of Gradient Orientation Module in HOG-based Human Detection System. In: 2017 IEEE Global Conference on Signal and Information Processing GlobalSIP 2017. Montreal: IEEE Signal Processing Society, 2017, pp. 1300-1304. ISBN 978-1-5090-5989-8.
 ČEKAN Ondřej and KOTÁSEK Zdeněk. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In: Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: TU Vienna, 2017, pp. 356-359. ISBN 978-1-5386-2146-2.
 ČUDOVÁ Marta. Framework for Planning, Running and Monitoring Cooperating Computations. In: Počítačové architektúry & diagnostika PAD 2017. Bratislava: Slovak University of Technology in Bratislava, 2017, pp. 20-23. ISBN 978-80-972784-0-3.

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