Ing. Zdeněk Vašíček, Ph.D.

2013Sekanina, L., Růžička, R., Vašíček, Z., Šimek, V., Hanáček, P.: Implementing a Unique Chip ID on a Reconfigurable Polymorphic Circuits, In: Information Technology And Control, Vol. 42, No. 1, 2013, Kaunas, LT, p. 7-14, ISSN 1392-124X
 Sekanina, L., Vašíček, Z.: Approximate Circuit Design by Means of Evolvable Hardware, In: 2013 IEEE International Conference on Evolvable Systems (ICES), Singapur, SG, IEEE CS, 2013, p. 21-28, ISBN 978-1-4673-5847-7
2012Bidlo, M., Vašíček, Z.: Cellular Automaton as a Sorting Network Generator Using Instruction-Based Development, In: Lecture Notes in Computer Science, Vol. 2012, No. 7495, DE, p. 214-223, ISSN 0302-9743
 Bidlo, M., Vašíček, Z.: Evolution of Cellular Automata Using Instruction-Based Approach, In: 2012 IEEE World Congress on Computational Intelligence, CA, US, IEEE, 2012, p. 1060-1067, ISBN 978-1-4673-1508-1
 Sekanina, L., Salajka, V., Vašíček, Z.: Two-Step Evolution of Polymorphic Circuits for Image Multi-Filtering, In: 2012 IEEE World Congress on Computational Intelligence, CA, US, IEEE, 2012, p. 432-439, ISBN 978-1-4673-1508-1
 Sekanina, L., Vašíček, Z.: A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits, In: Proc. of the 2012 Design, Automation and Test in Europe, Dresden, DE, EDAA, 2012, p. 715-720, ISBN 978-1-4577-2145-8
 Vašíček, Z., Sekanina, L.: On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming, In: 2012 IEEE World Congress on Computational Intelligence, CA, US, IEEE, 2012, p. 2379-2386, ISBN 978-1-4673-1508-1
 Vašíček, Z., Slaný, K.: Efficient Phenotype Evaluation in Cartesian Genetic Programming, In: Proc. of the 15th European Conference on Genetic Programming, Heidelberg, DE, Springer, 2012, p. 266-278, ISBN 978-3-642-29138-8
 Vašíček, Z.: Acceleration Methods for Evolutionary Design of Digital Circuits, Brno, CZ, 2012, p. 162
2011Dulík, T., Křivka, Z., Kadlec, J., Bližňák, M., Budíková, V., Jirák, O., Olšarová, N., Trbušek, J., Vašíček, Z.: Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA, Brno, CZ, CERM, 2011, p. 82, ISBN 978-80-7204-754-3
 Jirák, O., Křivka, Z., Vašíček, Z.: Integrated Development Environment for Virtual Laboratory, In: International Technology, Education and Development Conference, Valencia, ES, IATED, 2011, p. 10, ISBN 978-84-614-7423-3
 Křivka, Z., Vašíček, Z.: The Virtualization of Development Boards in the Virtual Laboratory of Microprocessor Technology, In: 12th International Carpathian Control Conference (ICCC), Velké Karlovice, CZ, VŠB TU, 2011, p. 424-428, ISBN 978-1-61284-359-9
 Sekanina, L., Vašíček, Z.: CGP Acceleration Using Field-Programmable Gate Arrays, Cartesian Genetic Programming, Berlin, DE, Springer, 2011, p. 217-230, ISBN 978-3-642-17309-7
 Vašíček, Z., Bidlo, M., Sekanina, L., Glette, K.: Evolutionary Design of Efficient and Robust Switching Image Filters, In: Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2011, p. 192-199, ISBN 978-1-4577-0599-1
 Vašíček, Z., Bidlo, M.: Evolutionary Design of Robust Noise-Specific Image Filters, In: 2011 IEEE Congress on Evolutionary Computation, New Orleans, US, IEEE CS, 2011, p. 269-276, ISBN 978-1-4244-7834-7
 Vašíček, Z., Sekanina, L.: A Global Postsynthesis Optimization Method for Combinational Circuits, In: Proc. of the Design, Automation and Test in Europe DATE 2011, Grenoble, FR, EDAA, 2011, p. 1525-1528, ISBN 978-3-9810801-7-9
 Vašíček, Z., Sekanina, L.: Evolutionary Optimization of Complex Digital Circuits, In: 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2011, p. 1, ISBN 978-80-214-4305-1
 Vašíček, Z., Sekanina, L.: Extensions of Cartesian Genetic Programming for Optimization of Complex Combinational Circuits, In: Proc. of the 20th International Workshop on Logic and Synthesis, San Diego, US, UCSD, 2011, p. 55-61
 Vašíček, Z., Sekanina, L.: Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware, In: Genetic Programming and Evolvable Machines, Vol. 12, No. 3, 2011, Berlin, DE, p. 305-327, ISSN 1389-2576
2010Bidlo, M., Slaný, K., Vašíček, Z.: Sorting Network Development Using Cellular Automata, In: Evolvable Systems: From Biology to Hardware, London, GB, Springer, 2010, p. 85-96, ISBN 978-3-642-15322-8
 Fišer, P., Schmidt, J., Vašíček, Z., Sekanina, L.: On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming, In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, p. 346-351, ISBN 978-1-4244-6610-8
 Jirák, O., Křivka, Z., Olšarová, N., Vašíček, Z.: Odvozování propojení komponent pro podporu návrhu pro malé FPGA čipy, In: DATAKON 2010 Proceedings (Ed. Petr Šaloun), Mikulov, CZ, Ostravská univerzita v Ostravě, 2010, p. 81-90, ISBN 978-80-7368-424-2
 Jirák, O., Křivka, Z., Vašíček, Z.: Component Interconnection Inference Tool Supporting the Design of Small FPGA-based Embedded Systems, In: Proceedings of the IADIS International Conference Applied Computing 2010, Timisoara, RO, IADIS Press, 2010, p. 230-234, ISBN 978-972-8939-30-4
 Vašíček, Z., Sekanina, L., Bidlo, M.: A Method for Design of Impulse Bursts Noise Filters Optimized for FPGA Implementations, In: DATE 2010: Design, Automation and Test in Europe, Dresden, DE, EDAA, 2010, p. 1731-1736, ISBN 978-3-9810801-6-2
 Vašíček, Z., Sekanina, L.: Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units, In: Computing and Informatics, Vol. 29, No. 6, 2010, Bratislava, SK, p. 1359-1371, ISSN 1335-9150
 Vašíček, Z.: Využití a akcelerace evolučních technik pro návrh číslicových obvodů, In: Počítačové architektury a diagnostika 2010, Brno, CZ, FIT VUT, 2010, p. 165-170, ISBN 978-80-214-4140-8
2009Bidlo, M., Vašíček, Z.: Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits, In: Proceedings 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, p. 423-430, ISBN 978-0-7695-3714-6
 Bidlo, M., Vašíček, Z.: Development of Combinational Circuits Using Non-Uniform Cellular Automata: Initial Results, In: Genetic and Evolutionary Computation, New York, US, ACM, 2009, p. 1839-1840, ISBN 978-1-60558-325-9
 Bidlo, M., Vašíček, Z.: Investigating Gate-Level Evolutionary Development of Combinational Multipliers Using Enhanced Cellular Automata-Based Model, In: Proc. of 2009 IEEE Congress on Evolutionary Computation, NA, US, IEEE CIS, 2009, p. 2241-2248, ISBN 978-1-4244-2958-5
 Sekanina, L., Růžička, R., Vašíček, Z., Prokop, R., Fujcik, L.: REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware, In: Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware, Nashville, US, IEEE CIS, 2009, p. 39-46, ISBN 978-1-4244-2755-0
 Sekanina, L., Vašíček, Z., Růžička, R., Bidlo, M., Jaroš, J., Švenda, P.: Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům, Praha, CZ, Academia, 2009, p. 328, ISBN 978-80-200-1729-1
 Vašíček, Z., Bidlo, M., Sekanina, L., Torresen, J., Glette, K., Furuholmen, M.: Evolution of Impulse Bursts Noise Filters, In: Proc. of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2009, p. 27-34, ISBN 978-0-7695-3714-6
 Vašíček, Z., Sekanina, L.: Efficient Hardware Accelerator for Symbolic Regression Problems, In: 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2009, p. 192-199, ISBN 978-80-87342-04-6
2008Bidlo, M., Vašíček, Z.: Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2008, p. 106-117, ISBN 978-3-540-85856-0
 Bidlo, M., Vašíček, Z.: Gate-Level Evolutionary Development Using Cellular Automata, In: 2008 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, ICSP, 2008, p. 11-18, ISBN 978-0-7695-3166-3
 Jirák, O., Křivka, Z., Vašíček, Z.: Debugging of Small FPGA-Based Embedded System, In: Proceedings of ASIS 2008, Ostrava, CZ, MARQ, 2008, p. 6, ISBN 978-80-86840-42-0
 Šimek, V., Vašíček, Z., Slaný, K.: Can the performance of GPGPU really beat CPU in evolutionary design task?, In: 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Znojmo, CZ, MUNI, 2008, p. 264-264, ISBN 978-80-7355-082-0
 Vašíček, Z., Čapka, L., Sekanina, L.: Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit, In: Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2008, p. 3-10, ISBN 978-0-7695-3166-3
 Vašíček, Z., Sekanina, L.: Hardware Accelerators for Cartesian Genetic Programming, In: Eleventh European Conference on Genetic Programming, Berlin, DE, Springer, 2008, p. 230-241, ISBN 978-3-540-78670-2
 Vašíček, Z., Sekanina, L.: Novel Hardware Implementation of Adaptive Median Filters, In: Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Bratislava, SK, IEEE CS, 2008, p. 110-115, ISBN 978-1-4244-2276-0
 Vašíček, Z., Žádník, M., Sekanina, L., Tobola, J.: On Evolutionary Synthesis of Linear Transforms, In: Evolvable Systems: From Biology > to > Hardware, Berlin, DE, Springer, 2008, p. 141-152, ISBN 978-3-540-85856-0
 Vašíček, Z.: Adaptivní hardware na bázi vyvíjejících se obvodů, In: Počítačové architektury a diagnostika 2008. Česko-slovenský seminář pro studenty doktorandského studia, Liberec, CZ, TUL, 2008, p. 119-124, ISBN 978-80-7372-378-1
 Vašíček, Z.: Towards Automatic Design of Competitive Image Filters in FPGAs, In: Proceedings of Junior Scientist Conference 2008, Vienna, AT, TU-Wien, 2008, p. 2, ISBN 978-3-200-01612-5
2007Čapka, L., Vašíček, Z.: Investigating the Influence of Mutation Operators in Cartesian Genetic Programming, In: 13th International Conference on Soft Computing, Brno, CZ, FSI VUT, 2007, p. 43-47, ISBN 978-80-214-3473-8
 Drahanský, M., Vašíček, Z.: Image stabilization in a video-stream, IDET 2007, Brno, CZ, EVPU, 2007, p. 1
 Vašíček, Z., Sekanina, L.: An Area-Efficient Alternative to Adaptive Median Filtering in FPGAs, In: Proc. of 2007 International Conference on Field Programmable Logic and Applications, Los Alamitos, US, IEEE CS, 2007, p. 216-221, ISBN 1424410606
 Vašíček, Z., Sekanina, L.: An Evolvable Hardware System in Xilinx Virtex II Pro FPGA, In: International Journal of Innovative Computing and Applications , Vol. 1, No. 1, 2007, Geneva, CH, p. 63-73, ISSN 1751-648X
 Vašíček, Z., Sekanina, L.: Evaluation of a New Platform For Image Filter Evolution, In: Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems, Los Alamitos, US, IEEE CS, 2007, p. 577-584, ISBN 076952866X
 Vašíček, Z., Sekanina, L.: Reducing the Area on a Chip Using a Bank of Evolved Filters, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2007, p. 222-232, ISBN 978-3-540-74625-6
 Vašíček, Z.: Reálné aplikace evolučního návrhu, In: Počítačové architektury a diagnostika 2007. Česko-slovenský seminář pro studenty doktorandského studia, Plzeň, CZ, ZČU v Plzni, 2007, p. 137-142, ISBN 978-80-7043-605-9
2006Sekanina, L., Vašíček, Z.: On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level, In: Applications of Evolutionary Computing, Berlin, DE, Springer, 2006, p. 344-355, ISBN 978-3-540-33237-4

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