Detail publikace

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

VAŠÍČEK Zdeněk a SEKANINA Lukáš. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, roč. 1, č. 1, 2007, s. 63-73. ISSN 1751-648X. Dostupné z: http://dx.doi.org/10.1504/IJICA.2007.013402
Název česky
An Evolvable Hardware System in Xilinx Virtex II Pro FPGA
Typ
článek v časopise
Jazyk
angličtina
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Abstrakt

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.  

Rok
2007
Strany
63-73
Časopis
International Journal of Innovative Computing and Applications, roč. 1, č. 1, ISSN 1751-648X
Vydavatel
Inderscience Publishers
DOI
EID Scopus
BibTeX
@ARTICLE{FITPUB8309,
   author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek and Luk\'{a}\v{s} Sekanina",
   title = "An Evolvable Hardware System in Xilinx Virtex II Pro FPGA",
   pages = "63--73",
   journal = "International Journal of Innovative Computing and Applications",
   volume = 1,
   number = 1,
   year = 2007,
   ISSN = "1751-648X",
   doi = "10.1504/IJICA.2007.013402",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/8309"
}
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