Most design automation methods developed for approximate computing evaluate candidate solutions by applying a set of input vectors and measuring the error of the output vectors with respect to an exact solution. This approach is not, however, applicable when approximating complex combinational or sequential circuits since the error is not computed precisely enough. This paper surveys various methods of formal verification that could be extended for purposes of determining the error of approximation more precisely and formulates this task through a notion of formal relaxed equivalence checking. |

@INPROCEEDINGS{
author = {Luk{\'{a}}{\v{s}} Hol{\'{i}}k and Ond{\v{r}}ej Leng{\'{a}}l
and Adam Rogalewicz and Luk{\'{a}}{\v{s}} Sekanina and
Zden{\v{e}}k Va{\v{s}}{\'{i}}{\v{c}}ek and Tom{\'{a}}{\v{s}}
Vojnar},
title = {Towards Formal Relaxed Equivalence Checking in Approximate
Computing Methodology},
pages = {1--6},
booktitle = {2nd Workshop on Approximate Computing (WAPCO 2016)},
year = {2016},
location = {Prague, },
language = {english},
url = {http://www.fit.vutbr.cz/research/view_pub.php.en.iso-8859-2?id=11008}
} |