Prof. Ing. Tomáš Vojnar, Ph.D.
Translator of VHDL Design to Counter Automaton |
| Authors: | Smrčka Aleš, Vojnar Tomáš |
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| Type: | software |
| Created: | 2007 |
| Licence: | required - no fee | | Files: | |
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| | Keywords: | VHDL, counter automata, translator, model, formal verification
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| Description: |
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The VHD2CA is the translator of a hardware desing in VHDL to a counter automaton. Some of modern tools for formal verification uses the counter automaton as the formalism for the description of an infinite state space model, thus the translation from VHDL to counter automaton allows the user to formal verify generic (parametric) hardware systems. The translator includes the whole LALR(1) grammar of VHDL'93 language and supports common used constructs.
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| Location: |
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| http://www.fit.vutbr.cz/~smrcka/projects/vhd2ca/ |
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| Licence terms: |
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| Free software under the terms of GNU GPL (cf. http://www.gnu.org/licenses/gpl.html). |
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Faculty of Information Technology
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