Towards Beneficial Hardware Acceleration of Functional Verification

Functional verification is a widespread technique to check whether a hardware design satisfies a given correctness specification. It is typically used in the pre-silicon phase of the design cycle to verify not only functional aspects but also reliability and safety properties. However, after the system is manufactured there are often found some previously uncovered errors. Moreover, further errors can be introduced by synthesis, mapping, place and route or fabrication processes. In order to eliminate as many remaining bugs as possible before a device is fabricated, verification is currently applied even in the post-silicon phase of the design cycle. Unfortunately, it is not possible to directly use the techniques from the pre-silicon phase (stimuli generation, assertion and coverage analysis, scoreboarding), and it is a challenging task to come up with techniques for post-silicon verification that would have
strength comparable to the pre-silicon ones. In the presentation, I will talk about how to handle the gap between pre- and post-silicon verification using hardware acceleration with functional verification features. Furthermore, I will present HAVEN, an open framework for hardware acceleration of functional verification that provides means for seamless transition from pre- to post-silicon verification.