Doc. Ing. František Vítězslav Zbořil, CSc.

Formal Approaches in Digital Design Diagnostics - Testable Design Verification
Reseach leader:Kotásek Zdeněk
Team leaders:Drábek Vladimír, Růžička Richard, Sekanina Lukáš, Strnadel Josef, Zbořil František
Agency:GAČR
Code:GA102/01/1531
Start:2001
End:2003
Keywords:testable design synthesis, digital circuit testability verification
Annotation:
The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topics of testability are evaluated simultaneously with the synthesis - e. g. full scan, partial scan or BIST methods. Different aspects of the circuit design are evaluated and the controllability/observability of the inputs/outputs of internal elements of the unit under design is an important feature. The diagnostic methodologies utilized during the circuit synthesis are based on heuristic approaches during which the structure of the circuit is analysed. These heuristic approaches are different for different types of circuits.The goal of this project is the development of formal tools which can be used to represent diagnostic features of a circuit and its internal elements, based on theory of sets, theory of graphs and mathematical logic concepts. The applicability of the formal tools will be verified on benchmark circuits and on circuits developed for practical applications. Together with this main theme the research into analytical approaches will be made. The results gained for both approaches will be currently compared. The possibility of combining both approaches will also be verified.

Publications

2004Strnadel Josef: Analýza a zlepšení testovatelnosti číslicového obvodu na úrovni meziregistrových přenosů, Brno, CZ, 2004, p. 150
2003Drábek Vladimír (editor): Montgomery Multiplication in GF(p) and GF(2^n), Brno, CZ, VUT v Brně, 2003, p. 106-109, ISBN 80-214-2452-4
 Kotásek Zdeněk, Mika Daniel, Strnadel Josef: Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems, In: Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems, Poznaň, PL, UNI-DRUK, 2003, p. 233-238, ISBN 83-7143-557-6
 Kotásek Zdeněk, Mika Daniel, Strnadel Josef: Test scheduling for embedded systems, In: Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003, Belek, TR, ICSP, 2003, p. 463-467, ISBN 0-7695-2003-0
 Kotásek Zdeněk, Růžička Richard, Sekanina Lukáš (editors): Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia, Brno, CZ, UPSY FIT VUT, 2003, p. 84, ISBN 80-214-2471-0
 Kotásek Zdeněk, Tupec Pavel, Urbiš Hynek: Testing PCBs Based on Boundary Scan, In: Proceedings of International Carpathian Control Conference, Košice, SK, TU v Košiciach, 2003, p. 119-122, ISBN 80-7099-509-2
 Kotásek Zdeněk, Urbiš Hynek: USB-to-IDE Adapter Design and Implementation, In: 6th International Workshopn on Electronics, Control, Measurment and Signals, Liberec, CZ, TUL, 2003, p. 315-319, ISBN 80-7083-708-X
 Mika Daniel, Kotásek Zdeněk: Proc. of IFAC Workshop on Programmable Devices and Systems Conference, In: Proc. of IFAC Workshop on Programmable Devices and Systems Conference, Ostrava, CZ, FEI VŠB, 2003, p. 447-452, ISBN 0-08-044130-0
 Mika Daniel: UPLATNĚNÍ FORMÁLNÍCH POSTUPŮ PŘI NÁVRHU ŘADIČE TESTU ČÍSLICOVÉHO OBVODU, In: Počítačové Architektury & Diagnostika Pracovní seminář pro studenty doktorského studia Sborník příspěvků, Brno, CZ, FIT VUT, 2003, p. 17-23, ISBN 80-214-2471-0
 Růžička Richard, Zbořil František: Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog, In: Proceedings of International Carpathian Control Conference, Košice, SK, TU v Košiciach, 2003, p. 727-730, ISBN 80-7099-509-2
 Růžička Richard: Testable Design Verification Using Petri Nets, In: Proceedings of Euromicro Symposium on Digital System Design 2003, Los Alamitos, CA, US, ICSP, 2003, p. 304-311, ISBN 0-7695-2003-0
 Sekanina Lukáš, Růžička Richard: Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers, In: The 2003 NASA/DoD Conference on Evolvable Hardware, Los Alamitos, US, ICSP, 2003, p. 135-144, ISBN 0-7695-1977-6
 Sekanina Lukáš, Růžička Richard: On the Automatic Design of Testable Circuits, In: Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems, Poznań, PL, UNI-DRUK, 2003, p. 299-300, ISBN 83-7143-557-6
 Sekanina Lukáš: Evolvable Components - From Theory to Hardware Implementations, Berlin, DE, Springer, 2003, p. 194, ISBN 3-540-40377-9
 Sekanina Lukáš: From Implementations to a General Concept of Evolvable Machines, In: Lecture Notes in Computer Science, Vol. 2003, No. 2610, DE, p. 424-433, ISSN 0302-9743
 Sekanina Lukáš: Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware, In: Lecture Notes in Computer Science, Vol. 2003, No. 2606, DE, p. 186-197, ISSN 0302-9743
 Sllame Azeddien M.: A Pipeline Scheduling Algorithm for High-Level Synthesis, In: Proc. of IFAC Workshop on Programmable Devices and Systems Conference, Ostrava, CZ, Elsevier, 2003, p. 178-183, ISBN 0-08-044130-0
 Strnadel Josef: Algebraic Analysis of Feedback Loop Dependencies in Order of Improving RTL Digital Circuit Testability, In: Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems, Poznan, PL, UNI-DRUK, 2003, p. 303-304, ISBN 83-7143-557-6
 Strnadel Josef: Analýza a zlepšení testovatelnosti RTL číslicového obvodu, In: Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika, Brno, CZ, FIT VUT, 2003, p. 24-29, ISBN 80-214-2471-0
 Strnadel Josef: Nested Loops Degree Impact on RTL Digital Circuit Testability, In: Programmable Devices and Systems, Oxford, GB, Elsevier, 2003, p. 202-207, ISBN 0-08-044130-0
 Strnadel Josef: Scan Layout Encoding by Means of a Binary String, In: Proceedings of 37th International Conference on Modelling and Simulation of Systems, Ostrava, CZ, MARQ, 2003, p. 115-122, ISBN 80-85988-86-0
2002Drábek Vladimír, Sekanina Lukáš: Basic Principles of Bio-Inspired Approaches to Fault Tolerance: Tutorial, In: Design for Test of Systems on Chip: Digital Test, Tallinn, EE, TTU, 2002, p. 1-48, ISBN 0000-00-000-0
 Hlavička Jan, Kotásek Zdeněk, Marinissen Erik Jan, Novák Ondřej, Růžička Richard, Straube Bernd (editors): Proceedings of 5th International Workshop IEEE Design and Diagnostics of Electronic Circuits and Systems, Brno, CZ, FIT VUT, 2002, p. 427, ISBN 80-214-2094-4
 Mika Daniel, Kotásek Zdeněk, Strnadel Josef: Test Controller Design Based on VHDL Source File Analysis, In: Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002, Letná 42, 040 01 TU Košice, SK, TU v Košiciach, 2002, p. 135-141, ISBN 80-7099-879-2
 Růžička Richard: Formální přístup k analýze testovatelnosti číslicových obvodů na úrovni RT, Brno, CZ, 2002, p. 102
 Růžička Richard: The Formal Approach to the RTL Test Application Problem Using Petri Nets, In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems 2002, Brno, CZ, FIT VUT, 2002, p. 78-86, ISBN 80-214-2094-4
 Růžička Richard: VHDL Circuit Description Transparency Analysis, In: Proceedings of the Fifth International Scientific Conference Electronic Computers and Informatics 2002, Košice, SK, FEI TU v Košiciach, 2002, p. 194-199, ISBN 80-7099-879-2
 Sekanina Lukáš, Drábek Vladimír: A Survey of Bioinspired Methods for Design of Fault Tolerant Reconfigurable Architectures, In: Proc. of the 8th Biennial Baltic Electronics Conference, Tallinn, EE, TTU, 2002, p. 355-358, ISBN 9985-59-292-1
 Sekanina Lukáš, Drábek Vladimír: Automatic Design of Image Operators Using Evolvable Hardware, In: Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Brno, CZ, VUT v Brně, 2002, p. 132-139, ISBN 80-214-2094-4
 Sekanina Lukáš, Drábek Vladimír: Soft-hardware, In: Vesmír, Vol. 81, No. 7, 2002, CZ, p. 393-395, ISSN 0042-4544
 Sekanina Lukáš: Automata of Evolvable Computational Machines, In: Proc. ot 8th conference Student EEICT, Brno, CZ, VUT v Brně, 2002, p. 491-495, ISBN 80-214-2116-9
 Sekanina Lukáš: Component Approach to Evolvable Systems, Brno, CZ, 2002, p. 132
 Sekanina Lukáš: Evolution of digital circuits operating as image filters in dynamically changing environment, In: Mendel 2002 - 8th International Conference on Soft Computing, Brno, CZ, VUT v Brně, 2002, p. 33-38, ISBN 80-214-2135-5
 Sekanina Lukáš: Evolvable Computational Machines: Formal Approach, In: Intelligent Technologies - Theory and Applications, E-ISCI 2002, Amsterdam, NL, IOS, 2002, p. 166-172, ISBN 1-58603-256-9
 Sekanina Lukáš: Image Filter Design with Evolvable Hardware, In: Lecture Notes in Computer Science, Vol. 2002, No. 2279, DE, p. 255-266, ISSN 0302-9743
 Sekanina Lukáš: Nanostructures and bio-inspired computer engineering (Abstract), In: Nano'02 (Abstracts), Brno, CZ, CERM, 2002, p. 74-74, ISBN 80-7204-258-0
 Sekanina Lukáš: Nanostructures and bio-inspired computer engineering, In: Proceedings of Nano02, Ostrava, CZ, Repronis, 2002, p. 233-236, ISBN 80-7329-027-8
 Sllame Azeddien M., Sekanina Lukáš: An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis, In: Advances in Nature-Inspired Computation: The PPSN VII Workshops, Reading, GB, PEDAL, 2002, p. 45-46, ISBN 0-9543481-0-9
 Sllame Azeddien M., Sekanina Lukáš: An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis, In: Mendel 2002 - 8th International Conference on Soft Computing, Brno, CZ, VUT v Brně, 2002, p. 87-92, ISBN 80-214-2135-5
 Strnadel Josef, Kotásek Zdeněk: Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level, In: Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002, Los Alamitos, US, ICSP, 2002, p. 166-173, ISBN 0-7695-1790-0
 Strnadel Josef: Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process, In: Proceeding of 8th Conference Student EEICT 2002, Brno, CZ, VUT v Brně, 2002, p. 506-510, ISBN 80-214-2116-9
 Zbořil František V., Kotásek Zdeněk, Mika Daniel, Strnadel Josef: The Identification of Feedback Loops in RTL Structures, In: Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002, Košice, CZ, TU v Košiciach, 2002, p. 142-147, ISBN 80-7099-879-2
2001Drábek Vladimír: Configurable Computing, In: Advanced Simulation of Systems, Ostrava, CZ, MARQ, 2001, p. 59-63, ISBN 80-85988-61-5
 Hlavička Jan, Kotásek Zdeněk, Růžička Richard, Strnadel Josef: Interactive Tool for Behavioral Level Testability Analysis, In: Proceedings of the IEEE ETW 2001, Stockholm, SE, 2001, p. 117-119
 Kotásek Zdeněk, Růžička Richard, Strnadel Josef, Zbořil František: Two Level Testability System, In: Proceedings of the 35th Spring International Conference MOSIS'01, Ostrava, CZ, MARQ, 2001, p. 433-440, ISBN 80-85988-57-7
 Kotásek Zdeněk, Růžička Richard, Strnadel Josef: Formal and Analytical Approaches to the Testability Analysis - the Comparison, In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001, Gyor, HU, SU, 2001, p. 123-128, ISBN 963-7175-16-4
 Kotásek Zdeněk, Strnadel Josef: Analytic Approach to RTL Testability Analysis, In: Proceedings of 7th Conference Student FEI 2001, Brno, CZ, VUT v Brně, 2001, p. 363-367, ISBN 80-214-1860-5
 Kotásek Zdeněk, Strnadel Josef: RTL Testability Analysis Based on Genetic Algorithm Implementation, In: Proceedings of the Tenth ICNACSA, Plovdiv, BG, neznámá, 2001, p. 1
 Kotásek Zdeněk, Strnadel Josef: RTL Testability Analysis Based on Genetic Algorithm Implementation, In: Proceedings of the IWCIT'01, Ostrava, CZ, FEI VŠB, 2001, p. 83-88, ISBN 80-7078-907-7
 Sllame Azeddien M., Drábek Vladimír: Specification and Synthesis of Reusable Modules in VHDL, In: Proceedings of fourth International Wokshop on IEEE Design and Diagnostics of Electronic Circuits and Systems IEEE DDCSE01, Gyor, Hungary, HU, SU, 2001, p. 137-140, ISBN 963-7175-16-4

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