Conference paper

MATOUŠEK Denis, KUBIŠ Juraj, MATOUŠEK Jiří and KOŘENEK Jan. Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks. In: Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems. Ithaca, NY: Association for Computing Machinery, 2018, pp. 104-110. ISBN 978-1-4503-5902-3.
Publication language:english
Original title:Regular Expression Matching with Pipelined Delayed Input DFAs for High-speed Networks
Title (cs):Vyhledávání vzorů popsaných regulárními výrazy za použití zřetězených automatů se zpožděným vstupem pro vysokorychlostní sítě
Pages:104-110
Proceedings:Proceedings of the 2018 Symposium on Architectures for Networking and Communications Systems
Conference:14th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '18)
Place:Ithaca, NY, US
Year:2018
ISBN:978-1-4503-5902-3
DOI:10.1145/3230718.3230730
Publisher:Association for Computing Machinery
Keywords
Regular expression matching, 100 Gbps, 400 Gbps, Delayed Input DFA, Pipelined automata
Annotation
Regular expression matching (RE matching) is a widely used operation in network security monitoring applications. With the speed of network links increasing to 100 Gbps and 400 Gbps, it is necessary to speed up packet processing and provide RE matching at such high speeds. Although many RE matching algorithms and architectures have been designed, none of them supports 100 Gbps throughput together with fast updates of an RE set. Therefore, this paper focuses on the design of a new hardware architecture that addresses both these requirements. The proposed architecture uses multiple highly memory-efficient Delayed Input DFAs (D2FAs), which are organized to a processing pipeline. As all D2FAs in the pipeline have only local communication, the proposed architecture is able to operate at high frequency even for a large number of parallel engines, which allows scaling throughput to hundreds of gigabits per second. The paper also analyses how to scale the number of engines and the capacity of buffers to achieve desired throughput. Using the parameters obtained while matching two sets of REs (represented by D2FAs) in a real network traffic, the architecture can be tuned for wire-speed throughput of 400 Gbps.
BibTeX:
@INPROCEEDINGS{
   author = {Denis Matou{\v{s}}ek and Juraj Kubi{\v{s}} and
	Ji{\v{r}}{\'{i}} Matou{\v{s}}ek and Jan
	Ko{\v{r}}enek},
   title = {Regular Expression Matching with Pipelined Delayed
	Input DFAs for High-speed Networks},
   pages = {104--110},
   booktitle = {Proceedings of the 2018 Symposium on Architectures for
	Networking and Communications Systems},
   year = {2018},
   location = {Ithaca, NY, US},
   publisher = {Association for Computing Machinery},
   ISBN = {978-1-4503-5902-3},
   doi = {10.1145/3230718.3230730},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en.iso-8859-2?id=11711}
}

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