Functional Verification of Digital Systems
|Ac.Year:||2018/2019 (Not opened)|
|Language of Instruction:||Czech|
|Guarantor:||Kotásek Zdeněk, doc. Ing., CSc. (DCSY)|
|Lecturer:||Zachariášová Marcela, Ing., Ph.D. (DCSY)|
|Instructor:||Zachariášová Marcela, Ing., Ph.D. (DCSY)|
|Faculty:||Faculty of Information Technology BUT|
|Department:||Department of Computer Systems FIT BUT|
| || ||Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.|
| || ||Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping.|
|Knowledge and skills required for the course:|
| || ||Digital system design, basic programming skills.|
|Subject specific learning outcomes and competencies:|
| || ||A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.|
|Generic learning outcomes and competencies:|
| || ||Acquired knowledge about the significance and possibilities of using functional verification methods within the development of digital systems and about their growing use in practice.||Why is the course taught:|
| || ||A demand for graduates with the knowledge of functional verification is still growing in the industry. The reason is that functional verification is a very important part of the development of digital systems. FVS is currently the only course in the Czech republic that is dealing with this topic. |
|Syllabus of lectures:|
- History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
- Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
- Introduction to functional verification. Functional verification techniques.
- Verification methodologies. HVL languages.
- Pseudo-random stimuli generation, direct tests, constraints.
- Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
- Self-checking mechanisms.
- Assertions. Assertion languages. Errors reporting.
- Assertion-based verification.
- Emulation and prototyping.
- Hardware debugging.
- Industry lecture.
- Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.
|Syllabus of laboratory exercises:|
- Creating testbench for a selected digital system.
- Creating verification environment for a selected digital system.
Coverage-driven verification of a selected digital system.
- Assertion-based verification of a selected digital system.
|Syllabus - others, projects and individual work of students:|
| ||Design and implementation of verification environment for a selected digital system.|
- Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
- Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217
- Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
- Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
- Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.
| ||Lecture notes in e-format.|
| || ||Labs and project in due dates.|
| || ||Requirements for class accreditation are not defined.|