Title:

Secure Hardware Devices

Code:BZA
Ac.Year:2019/2020
Sem:Summer
Curriculums:
ProgrammeField/
Specialization
YearDuty
IT-MSC-2MBI-Elective
IT-MSC-2MBS-Compulsory-Elective - group B
IT-MSC-2MGM-Elective
IT-MSC-2MIN-Compulsory-Elective - group B
IT-MSC-2MIS2ndCompulsory-Elective - group S
IT-MSC-2MMI-Elective
IT-MSC-2MMM-Elective
IT-MSC-2MPV-Elective
IT-MSC-2MSK-Elective
MITAINADE-Elective
MITAINBIO-Elective
MITAINCPS-Elective
MITAINEMB-Elective
MITAINGRI-Elective
MITAINHPC-Elective
MITAINIDE-Compulsory
MITAINISD-Elective
MITAINISY-Elective
MITAINMAL-Elective
MITAINMAT-Elective
MITAINNET-Elective
MITAINSEC2ndCompulsory
MITAINSEN-Elective
MITAINSPE-Elective
MITAINVER-Elective
MITAINVIZ-Elective
Language of Instruction:Czech
Credits:5
Completion:examination (written)
Type of
instruction:
Hour/semLecturesSeminar
Exercises
Laboratory
Exercises
Computer
Exercises
Other
Hours:3900013
 ExamsTestsExercisesLaboratoriesOther
Points:51200029
Guarantor:Hanáček Petr, doc. Dr. Ing. (DITS)
Deputy guarantor:Malinka Kamil, Mgr., Ph.D. (DITS)
Lecturer:Hanáček Petr, doc. Dr. Ing. (DITS)
Faculty:Faculty of Information Technology BUT
Department:Department of Intelligent Systems FIT BUT
Schedule:
DayLessonWeekRoomStartEndLect.Gr.Groups
WedlecturelecturesE104 13:0015:501MIT 2MIT xx
 
Learning objectives:
  The course applies knowledge acquired in the courses of Cryptography and Security of Information Systems (although they are not necessary prerequisite) in a particular area. It exends students' proficiency in implementation of secure and cryptographic devices. The goal is to make students search and analyse side-channels (unintended sources of information).
Description:
  The main goal of the introductory part is to overview existing secure hardware devices. This is leading us toward the area of side channels. A statement that implementation of a device without a side channel is infeasible is guiding us through topics of their seriousness and evaluation. The following part is dedicated to two important attacks on side channels: Timing and power analyses. Timing analysis is applicable not only on secure devices but also on software implementations of security protocols. The simplest secure devices are smart-cards and we go through their design, electrical properties, communication protocols, and overall security. Power and fault analyses are two other very powerful attacks on smart-cards and we dedicate a couple of lectures to their theoretical descriptions and examples of results obtainable through these techniques. The topic of mitigation of side-channels' capacities and especially TEMPEST follow. The last logical part of the lectures belongs to hardware security modules: Evolution, principal applications, definition of API, and attacks on API with demonstrations of common errors.
Subject specific learning outcomes and competencies:
  Theoretical and practical proficiency in design of secure information systems based on secure hardware devices. Ability to integrate secure devices (from smart-cards to hardware security modules) and identify weaknesses. Skill in thinking from an attacker's point of view and ability to use it for IS design. Theoretical and practical knowledge of essential attack categories.
Generic learning outcomes and competencies:
  Students start looking at information systems from an attacker's point of view. They also learn to identify potentially disasterous parts of information systems.
Why is the course taught:
  
This course is essential to all engineers working in the areas of computer engineering. Students will learn basic principles of information systems security and cryptography in hardware devices. 
Syllabus of lectures:
 
  • Introduction to secure hardware devices mentioning evolution, architectures, and applications. Random number generators (HW + SW).
  • Smart-cards - a lecture covering their design, electrical properties, communication protocols. Followed by their security properties and API security.
  • Side channels - their importance from the viewpoint of implementations, evaluations, and possible classification.
  • Timing analysis from its beginning in 1996 till actual implementations and performed attacks including detailed descriptions and definitions of the conditions necessary for its application.
  • Power and fault analyses represent powerful attacks on side channels available on smart-cards.
  • IoT security.
  • Half-term exam.
  • Nonarchitectural Attacks - Specter, Meltdown, Cache Abuse, Predictors, etc.
  • Student presentations on selected topics.
  • LFSR.
  • Protection of devices against side channels, various approaches to protection, principles, influence on the functionality of the devices.
  • Reverse Engineering - Techniques, Instruments, Examples.
  • Hardware security modules (HSM) and their evolution, main applications including examples of deployment and design of protocols based on HSMs.
Fundamental literature:
 
  • Cetin Kaya Koc: Cryptographic Engineering, Springer Publishing Company, 2008, ISBN: 0387718168 9780387718163
  • Menezes, A.J., van Oorschot, P., Vanstone, S.: Handbook of Applied Cryptography, CRC Press Series on Discrete Mathematics and Its Applications, Hardcover, 816 pages, CRC Press, 1997.
  • Bond, M. K.: Understanding Security APIs, PhD. thesis, Cambridge 2004.
  • Rankl, W., Effing, W.: Smart Card Handbook, John Wiley and Sons, pp. 1120, 3rd edition, 2004.
Study literature:
 
  • Cetin Kaya Koc: Cryptographic Engineering, Springer Publishing Company, 2008, ISBN: 0387718168 9780387718163
  • Menezes, A.J., van Oorschot, P., Vanstone, S.: Handbook of Applied Cryptography, CRC Press Series on Discrete Mathematics and Its Applications, Hardcover, 816 pages, CRC Press, 1997, available on http://www.cacr.math.uwaterloo.ca/hac/
  • Debdeep Mukhopadhyay, Rajat Subhra Chakraborty: Hardware Security: Design, Threats, and Safeguards, Chapman and Hall/CRC, 2014, ISBN 9781439895832
Progress assessment:
  Control of the study is performed via mid-term exam, completion of due course projects, and final exam. Evaluation of projects is based on the completeness and correctness of the delivered solutions.
 

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