Department of Intelligent Systems

Smart Application Aware Embedded Probes

Czech title:Vestavěné sondy pro analýzu a filtraci provozu na úrovni aplikačních protokolů
Research leader:Kořenek Jan
Team leaders:Korček Pavol, Žádník Martin
Team members:Dobai Roland, Košař Vlastimil, Puš Viktor (CESNET), Viktorin Jan
Agency:Ministry of Interior of the Czech Republic
Keywords:lawful interception, application protocol, probe, FPGA
The aim of the project is to create small and flexible network probes capable of lawful interception up to the application layer, to be used by the law enforcement agencies. The concept of software defined monitoring and the FPGA SoC computation platform will be used to achieve the required performance. The probe will, besides the detailed traffic analysis and filtering, provide statistical information and the information regarding the quality of the measured data. It will also identify the encrypted traffic and adjust the data acquisition to the available hardware resources.


2019Lawful Interception L7 Probe for 10 Gbps networks, specimen, 2019
Authors: Dražil Jan, Fukač Tomáš, Košař Vlastimil, Polčák Libor, Vrána Roman, Kekely Lukáš, Korček Pavol, Kořenek Jan
2018Hardware platform for network embedded devices with 10 Gbps network links, specimen, 2018
Authors: Sikora Jiří, Košař Vlastimil, Fukač Tomáš, Orsák Michal, Dražil Jan, Kořenek Jan
 Library of acceleration components for analysis of application-layer protocols on FPGA, software, 2018
Authors: Košař Vlastimil, Selecký Roman, Kořenek Jan, Fukač Tomáš
2017Lawful Interception L7 Probe, specimen, 2017
Authors: Dražil Jan, Fukač Tomáš, Kekely Lukáš, Košař Vlastimil, Polčák Libor, Korček Pavol, Kořenek Jan
 Packet Stack, software, 2017
Authors: Polčák Libor, Franková Barbora, Kekely Lukáš, Vrána Roman, Dražil Jan


2019FUKAČ Tomáš and KOŘENEK Jan. Hash-based Pattern Matching for High Speed Networks. In: 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019, pp. 1-5. ISBN 978-1-72810-073-9.
 VRÁNA Roman and KOŘENEK Jan. Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic. In: 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Cluj-Napoca: Institute of Electrical and Electronics Engineers, 2019, pp. 1-6. ISBN 978-1-72810-073-9.
2017KEKELY Michal and KOŘENEK Jan. Packet Classification with Limited Memory Resources. In: In proceedings 2017 Euromicro Conference on Digital System Design. Vieden: Institute of Electrical and Electronics Engineers, 2017, pp. 179-183. ISBN 978-1-5386-2145-5.
 KOŘENEK Jan and KEKELY Michal. Mapping of P4 Match Action Tables to FPGA. In: Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS. Ghent: Institute of Electrical and Electronics Engineers, 2017, pp. 1-2. ISBN 978-90-90-30428-1.
2016DOBAI Roland, KOŘENEK Jan and SEKANINA Lukáš. Adaptive Development of Hash Functions in FPGA-Based Network Routers. In: 2016 IEEE Symposium Series on Computational Intelligence. Athens: IEEE Computational Intelligence Society, 2016, pp. 1-8. ISBN 978-1-5090-4240-1.
 KOŠAŘ Vlastimil and KOŘENEK Jan. Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA. In: Proceedings of The 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016, pp. 591-598. ISBN 978-1-5090-2816-0.
 KOŘENEK Jan and VIKTORIN Jan. Packet Processing on FPGA SoC with DPDK. In: 26th International Conference on Field-Programmable Logic and Applications. Lausanne: École Polytechnique Fédérale de Lausanne, 2016, pp. 578-579. ISBN 978-2-8399-1844-2.

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