FITTest_BENCH06 Benchmarks & Cirgen


FITTest_BENCH06

The set consists of 31 circuits at various levels of complexity (2000, 10000, 28000, 100000, 150000 and 300000 gates). Four circuits with different diagnostic properties are available for each level of circuit complexity (fault coverage is approx. 0%, 33%, 66% and 100%). The benchmark circuits are available both at the register transfer level and the gate level.

What is cirgen?

Cirgen is RTL (Register Transfer level) benchmark circuit generator. It utilizes an evolutionary algorithm to design a structure of a benchmark circuits automatically according to the testability requirements specified by the user.

More information about cirgen

  • EH'05 contribution - The 2005 NASA/DoD Conference on Evolvable Hardware (pdf, ps)
  • ETS'04 contribution - 9th IEEE European Test Symposium (pdf, ps)

    Download

    File Description
    cirgen.zip Cirgen binary files (DOS, Winxx, WinXP)...
    cirgen_src.zip Cirgen source files...
    components.vhd Components library necessary to compile resulting VHDL files.

    FITTest_BENCH06

    Download all circuits (VHDL, Verilog, EDIF) in one archive  16,6MB

    FITTest_BENCH06(a)

    Variable complexity/variable diagnostic properties - 20 circuits with 5 levels of complexity - 2000, 10000, 28000, 150000 and 300000 gates. For each level of complexity, circuits at four levels of diagnostic properties exist (fault coverage approx. 0%; 33%, 66% and 100%).

     - e01 - 

     

    Simple easy testable circuit - consists of 5xADD(16bit), 5xSUB(16bit), 5xMUX2(16bit) components and 5 primary inputs and outputs.

    Information & download

     
    Name
    e01
    PI PO Gates FF
    86 80 1985 160
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 ao21 ao22 ao221 aoi21 aoi22 aoi221 aoi32 aoi322 aoi332
    # of comp. 4 48 1 1 2 61 1 4 1 1
     
    Type of comp. aoi332 buf04 buf16 dff inv01 inv02 mux21 nand02 nand03 nor02
    # of comp. 1 14 11 160 7 144 79 6 1 49
     
    Type of comp. nor02 oai21 oai22 oai221 oai222 oai32 oai33 or02 xnor2 xor2
    # of comp. 49 6 47 4 1 1 1 2 201 95
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 90.45% 86.83%
    Test coverage 94.95% 92.89%
    ATPG effectiveness 99.97% 99.96%

     

     - e02 - 

     

    Simple circuit - consists of 5xADD(16bit), 5xSUB(16bit), 5xMUX2(16bit) components and 5 primary inputs and outputs.

    Information & download

     
    Name
    e02
    PI PO Gates FF
    86 80 1657 144
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 ao21 ao32 aoi22 aoi222 aoi32 dff inv02 mux21 nand02
    # of comp. 4 42 16 59 16 4 144 100 21 6
     
    Type of comp. nand02 nor02 oai21 oai22 xnor2 xor2
    # of comp. 6 34 2 35 164 110
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 60.69% 58.94%
    Test coverage 63.37% 62.52%
    ATPG effectiveness 99.88% 99.88%

     

     - e03 - 

     

    Simple circuit - consists of 5xADD(16bit), 5xSUB(16bit), 5xMUX2(16bit) components and 5 primary inputs and outputs.

    Information & download

     
    Name
    e03
    PI PO Gates FF
    86 80 2046 160
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and04 ao21 ao22 ao32 aoi21 aoi22 aoi221 aoi222 aoi32
    # of comp. 11 1 30 2 9 5 64 1 6 7
     
    Type of comp. aoi32 aoi321 aoi322 aoi33 aoi332 buf04 buf16 dff inv01 inv02
    # of comp. 7 2 1 2 1 12 20 160 28 120
     
    Type of comp. inv02 mux21 nand02 nand03 nor02 nor03 oai21 oai22 oai222 oai32
    # of comp. 120 68 19 8 31 5 9 46 1 3
     
    Type of comp. oai32 oai33 oai332 or02 or03 xnor2 xor2
    # of comp. 3 4 1 3 1 173 120
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 39.43% 39.43%
    Test coverage 41.56% 42.15%
    ATPG effectiveness 99.51% 99.52%

     

     - e04 - 

     

    Simple hard to test circuit - consists of 5xADD(16bit), 5xSUB(16bit), 5xMUX2(16bit) components and 5 primary inputs and outputs.

    Information & download

     
    Name
    e04
    PI PO Gates FF
    86 80 2221 160
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 ao21 ao22 aoi21 aoi22 aoi221 aoi222 aoi32 aoi33 aoi332
    # of comp. 16 25 3 14 83 12 1 4 3 1
     
    Type of comp. aoi332 buf04 buf16 dff inv01 inv02 mux21 nand02 nand03 nor02
    # of comp. 1 18 34 160 38 167 107 13 1 48
     
    Type of comp. nor02 nor03 oai21 oai22 oai221 oai32 oai321 oai33 oai332 oai43
    # of comp. 48 3 6 49 3 4 3 4 1 1
     
    Type of comp. oai43 or02 or03 xnor2 xor2
    # of comp. 1 8 1 186 91
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 0.00% 0.00%
    Test coverage 0.00% 0.00%
    ATPG effectiveness 100.00% 100.00%

     

     - e05 - 

     

    Easy testable circuit - consists of 25xADD(16bit), 25xSUB(16bit), 25xMUX2(16bit) components and 10 primary inputs and outputs.

    Information & download

     
    Name
    e05
    PI PO Gates FF
    186 160 10011 792
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 ao21 ao22 ao32 aoi21 aoi22 aoi221 aoi222 aoi32
    # of comp. 52 5 202 8 3 14 262 5 1 18
     
    Type of comp. aoi32 aoi321 aoi322 aoi33 aoi332 aoi422 aoi43 buf02 buf04 buf16
    # of comp. 18 4 4 7 14 1 1 27 48 82
     
    Type of comp. buf16 dff inv01 inv02 mux21 nand02 nand03 nand04 nor02 nor03
    # of comp. 82 792 157 498 472 55 16 16 200 2
     
    Type of comp. nor03 nor04 oai21 oai22 oai221 oai222 oai32 oai321 oai322 oai33
    # of comp. 2 1 26 179 4 7 20 10 3 2
     
    Type of comp. oai33 oai332 oai422 or02 or03 or04 xnor2 xor2
    # of comp. 2 9 1 9 3 1 862 600
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 90.11% 86.81%
    Test coverage 94.73% 92.84%
    ATPG effectiveness 99.77% 99.74%

     

     - e06 - 

     

    Circuit with average testability. The circuit consists of 25xADD(16bit), 25xSUB(16bit), 25xMUX2(16bit) components and 10 primary inputs and outputs.

    Information & download

     
    Name
    e06
    PI PO Gates FF
    186 160 9999 831
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 ao21 ao22 ao221 ao32 aoi21 aoi22 aoi221 aoi222
    # of comp. 49 5 182 13 5 5 27 292 4 6
     
    Type of comp. aoi222 aoi32 aoi321 aoi322 aoi332 buf04 buf16 dff inv01 inv02
    # of comp. 6 20 6 3 7 39 22 831 142 449
     
    Type of comp. inv02 mux21 nand02 nand03 nand04 nor02 nor03 oai21 oai22 oai221
    # of comp. 449 444 47 6 4 205 7 26 210 1
     
    Type of comp. oai221 oai222 oai32 oai321 oai322 oai33 oai332 oai43 oai44 or02
    # of comp. 1 5 15 5 2 4 13 1 1 11
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 43.90% 41.74%
    Test coverage 45.78% 44.14%
    ATPG effectiveness 95.62% 96.17%

     

     - e07 - 

     

    Circuit with average testability. The circuit consists of 25xADD(16bit), 25xSUB(16bit), 25xMUX2(16bit) components and 10 primary inputs and outputs.

    Information & download

     
    Name
    e07
    PI PO Gates FF
    186 160 9894 785
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 ao21 ao22 ao221 ao32 aoi21 aoi22 aoi221 aoi222
    # of comp. 53 2 207 15 3 4 32 322 10 1
     
    Type of comp. aoi222 aoi32 aoi321 aoi322 aoi332 aoi422 buf04 buf16 dff inv01
    # of comp. 1 23 3 3 3 1 44 30 785 124
     
    Type of comp. inv01 inv02 mux21 nand02 nand03 nand04 nor02 nor03 oai21 oai22
    # of comp. 124 558 424 40 9 3 242 2 25 199
     
    Type of comp. oai22 oai221 oai222 oai32 oai321 oai322 oai332 or02 or03 or04
    # of comp. 199 10 1 14 6 6 6 26 6 1
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 22.87% 21.36%
    Test coverage 23.79% 22.49%
    ATPG effectiveness 85.95% 86.01%

     

     - e08 - 

     

    Circuit with low testability. The circuit consists of 25xADD(16bit), 25xSUB(16bit), 25xMUX2(16bit) components and 10 primary inputs and outputs.

    Information & download

     
    Name
    e08
    PI PO Gates FF
    186 160 9559 778
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 and04 ao21 ao22 ao221 ao32 aoi21 aoi22 aoi221
    # of comp. 34 1 1 141 10 2 2 26 300 9
     
    Type of comp. aoi221 aoi222 aoi32 aoi321 aoi322 aoi33 aoi332 buf02 buf04 buf16
    # of comp. 9 4 12 2 1 1 4 19 25 24
     
    Type of comp. buf16 dff inv01 inv02 mux21 nand02 nand03 nor02 oai21 oai22
    # of comp. 24 778 81 473 474 31 3 153 18 219
     
    Type of comp. oai22 oai221 oai32 oai321 oai322 oai33 oai332 oai422 oai43 oai44
    # of comp. 219 10 11 4 1 3 6 1 1 1
     
    Type of comp. oai44 or02 or03 xnor2 xor2
    # of comp. 1 12 3 840 649
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 0.00% 0.00%
    Test coverage 0.00% 0.00%
    ATPG effectiveness 96.33% 96.65%

     

     - e09 - 

     

    Circuit with high testability. The circuit consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 25xADD(16), 25xSUB(16), 25xMUX2(16), 25xMUL(16) components and 15 primary inputs and outputs.

    Information & download

     
    Name
    e09
    PI PO Gates FF
    211 192 28065 2020
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and04 ao21 ao22 aoi21 aoi22 aoi32 buf02 buf04 dff
    # of comp. 21 40 329 3 6 619 33 38 96 2020
     
    Type of comp. dff inv02 mux21 nand02 nand04 nor02 nor04 oai21 oai22 oai32
    # of comp. 2020 1650 2110 924 65 714 130 29 196 17
     
    Type of comp. oai32 or02 xnor2 xor2
    # of comp. 17 96 3551 1116
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 91.90% 89.52%
    Test coverage 95.43% 94.03%
    ATPG effectiveness 99.94% 99.93%

     

     - e10 - 

     

    Circuit with average testability. The circuit consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 25xADD(16), 25xSUB(16), 25xMUX2(16), 25xMUL(16) components and 15 primary inputs and outputs.

    Information & download

     
    Name
    e10
    PI PO Gates FF
    179 208 27853 1979
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 and04 ao21 ao22 aoi21 aoi22 aoi32 aoi321 aoi322
    # of comp. 25 1 42 364 14 19 579 23 1 1
     
    Type of comp. aoi322 aoi332 aoi43 buf02 buf04 buf16 dff inv01 inv02 mux21
    # of comp. 1 2 2 37 77 8 1979 27 1528 2102
     
    Type of comp. mux21 nand02 nand03 nand04 nor02 nor03 nor04 oai21 oai22 oai32
    # of comp. 2102 999 1 61 742 1 132 33 193 14
     
    Type of comp. oai32 oai33 oai332 oai43 or02 xnor2 xor2
    # of comp. 14 2 2 2 27 3499 1175
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 64.22% 62.89%
    Test coverage 66.53% 65.87%
    ATPG effectiveness 83.50% 84.01%

     

     - e11 - 

     

    Circuit with average testability. The circuit consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 25xADD(16), 25xSUB(16), 25xMUX2(16), 25xMUL(16) components and 15 primary inputs and outputs.

    Information & download

     
    Name
    e11
    PI PO Gates FF
    211 200 28231 2058
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 and04 ao21 ao22 aoi21 aoi22 aoi32 aoi321 aoi322
    # of comp. 35 7 38 340 13 28 576 25 7 6
     
    Type of comp. aoi322 aoi33 aoi332 aoi43 buf02 buf04 buf16 dff inv01 inv02
    # of comp. 6 4 6 1 37 86 18 2058 103 1489
     
    Type of comp. inv02 mux21 nand02 nand03 nand04 nor02 nor03 nor04 oai21 oai22
    # of comp. 1489 1944 953 12 60 798 7 140 43 247
     
    Type of comp. oai22 oai221 oai222 oai32 oai321 oai322 oai332 or02 or03 xnor2
    # of comp. 247 1 2 32 5 1 16 75 2 3487
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 27.46% 27.50%
    Test coverage 28.45% 28.82%
    ATPG effectiveness 83.68% 84.41%

     

     - e12 - 

     

    Circuit with low testability. The circuit consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 25xADD(16), 25xSUB(16), 25xMUX2(16), 25xMUL(16) components and 15 primary inputs and outputs.

    Information & download

     
    Name
    e12
    PI PO Gates FF
    203 208 28438 2106
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Circuit structrure (TSMC elements)

     
    Type of comp. and02 and03 and04 ao21 ao32 aoi21 aoi22 aoi222 aoi32 aoi321
    # of comp. 16 1 33 284 1 21 589 1 35 3
     
    Type of comp. aoi321 aoi322 aoi332 buf02 buf04 buf16 dff inv01 inv02 mux21
    # of comp. 3 2 4 51 95 14 2106 90 1479 2100
     
    Type of comp. mux21 nand02 nand03 nand04 nor02 nor03 nor04 oai21 oai22 oai221
    # of comp. 2100 888 8 57 829 1 136 32 196 1
     
    Type of comp. oai221 oai32 oai321 oai332 oai43 or02 xnor2 xor2
    # of comp. 1 22 2 4 2 55 3513 1145
     

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 0.00% 0.00%
    Test coverage 0.00% 0.00%
    ATPG effectiveness 96.63% 96.63%

     

     - e13 - 

     

    Circuit with high testability. The circuit consist of 50xADD(16), 50xSUB(16), 50xMUX2(16), 50xADD(32), 50xSUB(32), 50xMUX2(32), 50xMUL(16,32) components and 75 primary inputs and outputs.

    Information & download

     
    Name
    e13
    PI PO Gates FF
    1669 1904 155046 6304
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 89.38% n/a
    Test coverage 93.33% n/a
    ATPG effectiveness 96.27% n/a

     

     - e14 - 

     

    Circuit with medium testability. The circuit consist of 50xADD(16), 50xSUB(16), 50xMUX2(16), 50xADD(32), 50xSUB(32), 50xMUX2(32), 50xMUL(16,32) components and 75 primary inputs and outputs.

    Information & download

     
    Name
    e14
    PI PO Gates FF
    1621 1904 155380 6368
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 64.46% n/a
    Test coverage 67.29% n/a
    ATPG effectiveness 74.39% n/a

     

     - e15 - 

     

    Circuit with medium testability. The circuit consist of 50xADD(16), 50xSUB(16), 50xMUX2(16), 50xADD(32), 50xSUB(32), 50xMUX2(32), 50xMUL(16,32) components and 75 primary inputs and outputs.

    Information & download

     
    Name
    e15
    PI PO Gates FF
    1701 1840 155207 6368
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 31.84% n/a
    Test coverage 33.24% n/a
    ATPG effectiveness 44.28% n/a

     

     - e16 - 

     

    Circuit with low testability. The circuit consist of 50xADD(16), 50xSUB(16), 50xMUX2(16), 50xADD(32), 50xSUB(32), 50xMUX2(32), 50xMUL(16,32) components and 75 primary inputs and outputs.

    Information & download

     
    Name
    e16
    PI PO Gates FF
    1589 1744 155045 6368
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 12.50% n/a
    Test coverage 13.05% n/a
    ATPG effectiveness 38.18% n/a

     

     - e17 - 

     

    Circuit with high testability. The circuit consist of 100xADD(16), 100xSUB(16), 100xMUX2(16), 100xADD(32), 100xSUB(32), 100xMUX2(32), 100xMUL(16,32) components and 180 primary inputs and outputs.

    Information & download

     
    Name
    e17
    PI PO Gates FF
    3833 4272 310122 12672
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 81.73% n/a
    Test coverage 85.32% n/a
    ATPG effectiveness 87.81% n/a

     

     - e18 - 

     

    Circuit with medium testability. The circuit consist of 100xADD(16), 100xSUB(16), 100xMUX2(16), 100xADD(32), 100xSUB(32), 100xMUX2(32), 100xMUL(16,32) components and 180 primary inputs and outputs.

    Information & download

     
    Name
    e18
    PI PO Gates FF
    3913 4512 309856 12608
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 56.72% n/a
    Test coverage 58.78% n/a
    ATPG effectiveness 62.12% n/a

     

     - e19 - 

     

    Circuit with medium testability. The circuit consist of 100xADD(16), 100xSUB(16), 100xMUX2(16), 100xADD(32), 100xSUB(32), 100xMUX2(32), 100xMUL(16,32) components and 180 primary inputs and outputs.

    Information & download

     
    Name
    e19
    PI PO Gates FF
    3833 4320 309874 12576
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 40.28% n/a
    Test coverage 42.05% n/a
    ATPG effectiveness 59.24% n/a

     

     - e20 - 

     

    Circuit with low testability. The circuit consist of 100xADD(16), 100xSUB(16), 100xMUX2(16), 100xADD(32), 100xSUB(32), 100xMUX2(32), 100xMUL(16,32) components and 180 primary inputs and outputs.

    Information & download

     
    Name
    e20
    PI PO Gates FF
    3961 4352 310610 12736
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF

    Testability results by FlexTest

     
      Uncollapsed Collapsed
    Fault coverage 23.13% n/a
    Test coverage 24.14% n/a
    ATPG effectiveness 46.07% n/a

     

    FITTest_BENCH06(b)

    Constant complexity/variable diagnostic properties - 11 synthetic benchmarks with identical complexity but different diagnostic properties. All eleven circuits have 35 primary inputs, 35 primary outputs and consist of 35x16-bit adders, 35x16-bit subtractors, 35x16-bit multiplexers, 35x32-bit adders, 35x32-bit subtractors, 35x32-bit multiplexers, 35x16/32 multipliers and 175x(16/32)-bit registers. For each circuit, different controllability and observability is available in range from 0% to 100%.

     - a01 - 

     

    Information & download

     
    Name
    a01
    PI PO Gates FF
    839 880 108748 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a02 - 

     

    Information & download

     
    Name
    a02
    PI PO Gates FF
    775 816 108532 4416
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a03 - 

     

    Information & download

     
    Name
    a03
    PI PO Gates FF
    775 912 108876 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a04 - 

     

    Information & download

     
    Name
    a04
    PI PO Gates FF
    791 912 108551 4416
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a05 - 

     

    Information & download

     
    Name
    a05
    PI PO Gates FF
    775 848 108740 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a06 - 

     

    Information & download

     
    Name
    a06
    PI PO Gates FF
    775 896 108607 4416
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a07 - 

     

    Information & download

     
    Name
    a07
    PI PO Gates FF
    743 848 108811 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a08 - 

     

    Information & download

     
    Name
    a08
    PI PO Gates FF
    839 992 108650 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a09 - 

     

    Information & download

     
    Name
    a09
    PI PO Gates FF
    743 944 108345 4384
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

     - a10 - 

     

    Information & download

     
    Name
    a10
    PI PO Gates FF
    775 832 108652 4448
    RTL Gate level EDIF ZIP
    VHDL VHDL Verilog EDIF
     

    Old circuits

    Benchmark set Description

    Circuits consist of 5xADD(8), 5xSUB(8), 5xMUX2(8), 5 primary inputs and outputs. Each set contains 10 circuits.

    circuits_a01.zip testability: high (controllability~90%, observability~90%)
    circuits_a02.zip testability: medium (controllability~50%, observability~50%)
    circuits_a03.zip testability: low (controllability~10%, observability~10%)

    Circuits consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 10 primary inputs and outputs. Each set contains 10 circuits.

    circuits_b01.zip testability: high (controllability~90%, observability~90%)
    circuits_b02.zip testability: medium (controllability~50%, observability~50%)
    circuits_b03.zip testability: low (controllability~10%, observability~10%)

    Circuits consist of 25xADD(8), 25xSUB(8), 25xMUX2(8), 25xADD(16), 25xSUB(16), 25xMUX2(16), 25xMUL(16), 15 primary inputs and outputs. Each set contains 10 circuits.

    circuits_c01.zip testability: high (controllability~90%, observability~90%)
    circuits_c02.zip testability: medium (controllability~50%, observability~50%)
    circuits_c03.zip testability: low (controllability~10%, observability~10%)