Download Verilog module definition
Include accurate
Area | from to |
Delay | from to |
Power | from to |
MRE | from to |
EP | from to |
Circuit | Area (45) | Delay (45) | Power (45) | MAE | MRE | WCE LIMIT | WCE LIMIT % | EP | OPS |
---|---|---|---|---|---|---|---|---|---|
mul32x32_000 | 14988 μm2 | 4.470 ns | 10.46 mW | 15050284408.9 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_001 | 13069 μm2 | 4.530 ns | 9.07 mW | 21632574174.3 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_002 | 14758 μm2 | 4.030 ns | 10.38 mW | 25377300389.6 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_003 | 15629 μm2 | 4.410 ns | 11.31 mW | 16217300735.9 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_004 | 14601 μm2 | 4.190 ns | 10.30 mW | 23048418156.7 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_005 | 16918 μm2 | 4.350 ns | 11.93 mW | 21675480530.9 | 0.00 % | 1844674407370955 | 0.000001 % | 100.0 % | Verilog C |
mul32x32_006 | 13484 μm2 | 3.900 ns | 9.32 mW | 54818640823.1 | 0.00 % | 3689348814741910 | 0.000002 % | 100.0 % | Verilog C |
mul32x32_007 | 10455 μm2 | 3.970 ns | 7.45 mW | 47327050528.7 | 0.00 % | 3689348814741910 | 0.000002 % | 100.0 % | Verilog C |
mul32x32_008 | 13376 μm2 | 4.230 ns | 9.32 mW | 36016846500.0 | 0.00 % | 3689348814741910 | 0.000002 % | 100.0 % | Verilog C |
mul32x32_009 | 12797 μm2 | 3.910 ns | 8.31 mW | 251310691837.5 | 0.00 % | 18446744073709552 | 0.00001 % | 100.0 % | Verilog C |
mul32x32_010 | 14170 μm2 | 3.800 ns | 9.33 mW | 262513246761.7 | 0.00 % | 18446744073709552 | 0.00001 % | 100.0 % | Verilog C |
mul32x32_011 | 9852 μm2 | 3.790 ns | 6.59 mW | 373399490584.2 | 0.00 % | 36893488147419104 | 0.00002 % | 100.0 % | Verilog C |
mul32x32_012 | 5992 μm2 | 3.450 ns | 4.85 mW | 591810484274.2 | 0.00 % | 36893488147419104 | 0.00002 % | 100.0 % | Verilog C |
mul32x32_013 | 16000 μm2 | 3.660 ns | 11.23 mW | 553756233119.8 | 0.00 % | 36893488147419104 | 0.00002 % | 100.0 % | Verilog C |
mul32x32_014 | 10425 μm2 | 3.430 ns | 6.97 mW | 619872635900.1 | 0.00 % | 36893488147419104 | 0.00002 % | 100.0 % | Verilog C |
mul32x32_015 | 6380 μm2 | 3.420 ns | 4.68 mW | 897226394882.7 | 0.00 % | 92233720368547760 | 0.00005 % | 100.0 % | Verilog C |
mul32x32_016 | 5560 μm2 | 3.190 ns | 4.32 mW | 979960893535.9 | 0.00 % | 92233720368547760 | 0.00005 % | 100.0 % | Verilog C |
mul32x32_017 | 5501 μm2 | 3.580 ns | 4.59 mW | 2138212916832.5 | 0.00 % | 92233720368547760 | 0.00005 % | 100.0 % | Verilog C |
mul32x32_018 | 6176 μm2 | 3.220 ns | 4.32 mW | 2284237534128.5 | 0.01 % | 184467440737095520 | 0.0001 % | 100.0 % | Verilog C |
mul32x32_019 | 4247 μm2 | 3.530 ns | 3.50 mW | 5020875852735.8 | 0.06 % | 368934881474191040 | 0.0002 % | 100.0 % | Verilog C |
mul32x32_020 | 4011 μm2 | 2.940 ns | 3.23 mW | 10223441675419.9 | 0.02 % | 922337203685477632 | 0.0005 % | 100.0 % | Verilog C |
mul32x32_021 | 4020 μm2 | 2.890 ns | 3.20 mW | 8393005615588.2 | 0.02 % | 922337203685477632 | 0.0005 % | 100.0 % | Verilog C |
mul32x32_022 | 4143 μm2 | 2.720 ns | 3.25 mW | 11061329579902.1 | 0.03 % | 922337203685477632 | 0.0005 % | 100.0 % | Verilog C |
mul32x32_023 | 3871 μm2 | 3.040 ns | 3.13 mW | 13579965158018.1 | 0.05 % | 922337203685477632 | 0.0005 % | 100.0 % | Verilog C |
mul32x32_024 | 3842 μm2 | 3.020 ns | 3.17 mW | 19256420493183.3 | 0.04 % | 922337203685477632 | 0.0005 % | 100.0 % | Verilog C |
mul32x32_025 | 4142 μm2 | 3.050 ns | 3.11 mW | 25599997588284.2 | 0.07 % | 1844674407370955264 | 0.001 % | 100.0 % | Verilog C |
mul32x32_026 | 3613 μm2 | 3.080 ns | 2.82 mW | 25915162935397.0 | 0.07 % | 1844674407370955264 | 0.001 % | 100.0 % | Verilog C |
mul32x32_027 | 3844 μm2 | 2.920 ns | 2.74 mW | 47095856567719.1 | 0.09 % | 3689348814741910528 | 0.002 % | 100.0 % | Verilog C |
mul32x32_028 | 3947 μm2 | 2.990 ns | 2.77 mW | 33511556401385.6 | 0.08 % | 3689348814741910528 | 0.002 % | 100.0 % | Verilog C |
mul32x32_029 | 3697 μm2 | 2.940 ns | 2.72 mW | 44584428242002.3 | 0.10 % | 3689348814741910528 | 0.002 % | 100.0 % | Verilog C |
mul32x32_030 | 3210 μm2 | 2.280 ns | 2.51 mW | 55021749617028.0 | 0.17 % | 3689348814741910528 | 0.002 % | 100.0 % | Verilog C |
mul32x32_031 | 3460 μm2 | 3.010 ns | 2.60 mW | 46726676440979.7 | 0.12 % | 3689348814741910528 | 0.002 % | 100.0 % | Verilog C |
mul32x32_032 | 2912 μm2 | 2.750 ns | 2.21 mW | 162545951608376.5 | 0.31 % | 9223372036854775808 | 0.005 % | 100.0 % | Verilog C |
mul32x32_033 | 3063 μm2 | 2.550 ns | 2.27 mW | 153038649913872.0 | 0.28 % | 9223372036854775808 | 0.005 % | 100.0 % | Verilog C |
mul32x32_034 | 3129 μm2 | 2.630 ns | 2.34 mW | 149059810610824.8 | 0.26 % | 9223372036854775808 | 0.005 % | 100.0 % | Verilog C |
mul32x32_035 | 2795 μm2 | 2.750 ns | 2.15 mW | 165344952926952.1 | 0.34 % | 9223372036854775808 | 0.005 % | 100.0 % | Verilog C |
mul32x32_036 | 2839 μm2 | 2.700 ns | 2.17 mW | 157635011266171.3 | 0.38 % | 9223372036854775808 | 0.005 % | 100.0 % | Verilog C |
mul32x32_037 | 3280 μm2 | 2.630 ns | 2.22 mW | 199909608383594.0 | 0.41 % | 18446744073709551616 | 0.01 % | 100.0 % | Verilog C |
mul32x32_038 | 2707 μm2 | 2.680 ns | 1.97 mW | 215357919932424.7 | 0.32 % | 18446744073709551616 | 0.01 % | 100.0 % | Verilog C |
mul32x32_039 | 3040 μm2 | 2.440 ns | 2.20 mW | 245913139314778.3 | 0.49 % | 18446744073709551616 | 0.01 % | 100.0 % | Verilog C |
mul32x32_040 | 3138 μm2 | 2.260 ns | 2.18 mW | 296232352067075.3 | 0.48 % | 18446744073709551616 | 0.01 % | 100.0 % | Verilog C |
mul32x32_041 | 2613 μm2 | 2.570 ns | 1.88 mW | 332807992140700.0 | 0.66 % | 18446744073709551616 | 0.01 % | 100.0 % | Verilog C |
mul32x32_042 | 2307 μm2 | 2.190 ns | 1.71 mW | 488554375104327.1 | 0.93 % | 36893488147419103232 | 0.02 % | 100.0 % | Verilog C |
mul32x32_043 | 2317 μm2 | 2.440 ns | 1.63 mW | 637576788074157.1 | 1.45 % | 36893488147419103232 | 0.02 % | 100.0 % | Verilog C |
mul32x32_044 | 2212 μm2 | 2.450 ns | 1.60 mW | 641053997365433.4 | 1.25 % | 36893488147419103232 | 0.02 % | 100.0 % | Verilog C |
mul32x32_045 | 2219 μm2 | 2.270 ns | 1.39 mW | 696507083600187.4 | 3.26 % | 92233720368547758080 | 0.05 % | 100.0 % | Verilog C |
mul32x32_046 | 2049 μm2 | 2.460 ns | 1.38 mW | 868849187577007.9 | 2.24 % | 92233720368547758080 | 0.05 % | 100.0 % | Verilog C |
mul32x32_047 | 1867 μm2 | 2.270 ns | 1.24 mW | 1201160722090766.8 | 4.84 % | 92233720368547758080 | 0.05 % | 100.0 % | Verilog C |
mul32x32_048 | 1922 μm2 | 2.580 ns | 1.31 mW | 1015064664890547.8 | 2.75 % | 92233720368547758080 | 0.05 % | 100.0 % | Verilog C |
mul32x32_049 | 2134 μm2 | 2.200 ns | 1.39 mW | 1208466017512107.8 | 3.62 % | 92233720368547758080 | 0.05 % | 100.0 % | Verilog C |
mul32x32_050 | 2151 μm2 | 2.340 ns | 1.45 mW | 1540520509828062.2 | 1.82 % | 184467440737095516160 | 0.1 % | 100.0 % | Verilog C |
mul32x32_051 | 1714 μm2 | 2.210 ns | 1.14 mW | 1500040826856874.0 | 3.89 % | 184467440737095516160 | 0.1 % | 100.0 % | Verilog C |
mul32x32_052 | 1589 μm2 | 2.090 ns | 1.06 mW | 3337602853479244.5 | 9.14 % | 184467440737095516160 | 0.1 % | 100.0 % | Verilog C |
mul32x32_053 | 1576 μm2 | 2.030 ns | 1.05 mW | 3108264620885303.0 | 10.59 % | 184467440737095516160 | 0.1 % | 100.0 % | Verilog C |
mul32x32_054 | 2018 μm2 | 1.950 ns | 1.10 mW | 3442068564982690.0 | 7.90 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_055 | 1648 μm2 | 2.020 ns | 1.02 mW | 4017833557107765.5 | 8.19 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_056 | 1574 μm2 | 2.130 ns | 0.93 mW | 4805375431599626.0 | 13.50 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_057 | 1478 μm2 | 2.060 ns | 0.88 mW | 4485281687646734.5 | 14.04 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_058 | 1344 μm2 | 2.210 ns | 0.84 mW | 6655932388662105.0 | 17.16 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_059 | 1366 μm2 | 1.980 ns | 0.87 mW | 5611539629342099.0 | 15.22 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_060 | 1513 μm2 | 2.120 ns | 0.97 mW | 4824115491890895.0 | 10.92 % | 368934881474191032320 | 0.2 % | 100.0 % | Verilog C |
mul32x32_061 | 1150 μm2 | 1.750 ns | 0.69 mW | 10647482012080490.0 | 19.69 % | 922337203685477580800 | 0.5 % | 100.0 % | Verilog C |
mul32x32_062 | 1083 μm2 | 1.870 ns | 0.65 mW | 14784666561960574.0 | 33.88 % | 922337203685477580800 | 0.5 % | 100.0 % | Verilog C |
mul32x32_063 | 1141 μm2 | 1.770 ns | 0.69 mW | 15222148331255044.0 | 29.43 % | 922337203685477580800 | 0.5 % | 100.0 % | Verilog C |
mul32x32_064 | 1125 μm2 | 1.910 ns | 0.66 mW | 14259448732928656.0 | 33.21 % | 922337203685477580800 | 0.5 % | 100.0 % | Verilog C |
mul32x32_065 | 1311 μm2 | 1.650 ns | 0.71 mW | 14523504718189976.0 | 31.53 % | 922337203685477580800 | 0.5 % | 100.0 % | Verilog C |
mul32x32_066 | 1022 μm2 | 1.740 ns | 0.56 mW | 23024975278174052.0 | 60.41 % | 1844674407370955161600 | 1 % | 100.0 % | Verilog C |
mul32x32_067 | 869 μm2 | 1.750 ns | 0.51 mW | 25343988977096948.0 | 41.25 % | 1844674407370955161600 | 1 % | 100.0 % | Verilog C |
mul32x32_068 | 879 μm2 | 1.650 ns | 0.53 mW | 32770457350171664.0 | 61.04 % | 1844674407370955161600 | 1 % | 100.0 % | Verilog C |
mul32x32_069 | 808 μm2 | 1.760 ns | 0.48 mW | 35262162734031276.0 | 59.90 % | 1844674407370955161600 | 1 % | 100.0 % | Verilog C |
mul32x32_070 | 901 μm2 | 1.660 ns | 0.51 mW | 32427288552322236.0 | 73.00 % | 1844674407370955161600 | 1 % | 100.0 % | Verilog C |
mul32x32_071 | 844 μm2 | 1.680 ns | 0.45 mW | 37548190765104584.0 | 87.53 % | 3689348814741910323200 | 2 % | 100.0 % | Verilog C |
mul32x32_072 | 794 μm2 | 1.620 ns | 0.46 mW | 43916470950142072.0 | 89.18 % | 3689348814741910323200 | 2 % | 100.0 % | Verilog C |
mul32x32_073 | 647 μm2 | 1.510 ns | 0.36 mW | 70287410808033720.0 | 145.02 % | 3689348814741910323200 | 2 % | 100.0 % | Verilog C |
mul32x32_074 | 737 μm2 | 1.640 ns | 0.39 mW | 51008789241174568.0 | 107.69 % | 3689348814741910323200 | 2 % | 100.0 % | Verilog C |
mul32x32_075 | 497 μm2 | 1.390 ns | 0.24 mW | 165259360231995424.0 | 1190.48 % | 9223372036854775808000 | 5 % | 100.0 % | Verilog C |
mul32x32_076 | 517 μm2 | 1.320 ns | 0.25 mW | 132783207020258064.0 | 304.62 % | 9223372036854775808000 | 5 % | 100.0 % | Verilog C |
mul32x32_077 | 479 μm2 | 1.430 ns | 0.23 mW | 116565409620054176.0 | 241.23 % | 9223372036854775808000 | 5 % | 100.0 % | Verilog C |
mul32x32_078 | 500 μm2 | 1.300 ns | 0.23 mW | 174083938059875456.0 | 1490.78 % | 9223372036854775808000 | 5 % | 100.0 % | Verilog C |
mul32x32_079 | 319 μm2 | 1.290 ns | 0.13 mW | 296427084392260992.0 | 731.18 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_080 | 305 μm2 | 1.070 ns | 0.13 mW | 307645601825800128.0 | 585.51 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_081 | 369 μm2 | 1.240 ns | 0.15 mW | 316764147389671488.0 | 569.82 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_082 | 288 μm2 | 1.080 ns | 0.14 mW | 309229898834196672.0 | 642.42 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_083 | 341 μm2 | 1.220 ns | 0.15 mW | 319409186504226880.0 | 580.58 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_084 | 322 μm2 | 1.230 ns | 0.13 mW | 318483583594199872.0 | 644.20 % | 18446744073709551616000 | 10 % | 100.0 % | Verilog C |
mul32x32_085 | 211 μm2 | 0.850 ns | 0.08 mW | 347225110390225728.0 | 672.55 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_086 | 206 μm2 | 0.880 ns | 0.07 mW | 463088604825126784.0 | 1086.93 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_087 | 204 μm2 | 0.890 ns | 0.07 mW | 479504607215923136.0 | 1109.70 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_088 | 175 μm2 | 0.770 ns | 0.05 mW | 550417964720168512.0 | 1382.20 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_089 | 204 μm2 | 0.760 ns | 0.07 mW | 467288168949157952.0 | 2837.06 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_090 | 211 μm2 | 1.030 ns | 0.08 mW | 396041399581342208.0 | 721.10 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_091 | 164 μm2 | 0.800 ns | 0.05 mW | 558019923315181184.0 | 1253.97 % | 27670116110564327424000 | 15 % | 100.0 % | Verilog C |
mul32x32_092 | 214 μm2 | 0.800 ns | 0.08 mW | 292263837371712192.0 | 165.05 % | 27670116110564327424000 | 15 % | 96.9 % | Verilog C |
mul32x32_093 | 157 μm2 | 0.780 ns | 0.05 mW | 590210709363001216.0 | 1329.46 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |
mul32x32_094 | 146 μm2 | 0.700 ns | 0.04 mW | 567238759059361728.0 | 1428.07 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |
mul32x32_095 | 172 μm2 | 0.930 ns | 0.06 mW | 563815939743124608.0 | 752.91 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |
mul32x32_096 | 138 μm2 | 0.680 ns | 0.04 mW | 585785359732371840.0 | 1473.69 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |
mul32x32_097 | 134 μm2 | 0.830 ns | 0.04 mW | 640158727941016320.0 | 1642.29 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |
mul32x32_098 | 134 μm2 | 0.630 ns | 0.04 mW | 638204913282206336.0 | 1557.34 % | 36893488147419103232000 | 20 % | 100.0 % | Verilog C |