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00043 #ifndef _MODEL_H_
00044 #define _MODEL_H_
00045
00046 #include <set>
00047 #include <map>
00048 #include <string>
00049 #include <iostream>
00050 #include <sstream>
00051
00052 #include "expressionevaluator/ExpressionEvaluator.h"
00053 #include "fileio.h"
00054 #include "misc.h"
00055 #include "stringtokenizer/StringTokenizer.h"
00056
00057 using namespace std;
00058
00059 extern bool debug_mode;
00060 extern unsigned long nerrors;
00061
00062 #include "defs.h"
00063 #include "error.h"
00064
00065
00066
00067
00069 typedef enum tmodeSel {CON_MODE, OBS_MODE, TST_MODE};
00070
00071
00072
00073
00081 typedef struct mTypeData
00082 {
00083 string from_name;
00084 string to_name;
00085 string cond;
00086 string composed;
00087 bool orig;
00088 }
00089 tMTypeData;
00090
00092 struct lt_mtdata
00093 {
00094 bool operator()(const tMTypeData d1, const tMTypeData d2) const
00095 {
00096 return (d1.composed < d2.composed);
00097 }
00098 };
00099
00100
00101
00102
00110 class clsModuleType
00111 {
00112
00113 string name;
00114 string area;
00115 string power;
00116 set<tMTypeData, lt_mtdata> setOfTRANIS;
00117 set<string> setOfPorts;
00118
00119 public:
00120
00121 clsModuleType(string nm){ name=nm; }
00122 ~clsModuleType(){;}
00123
00124 bool operator<(clsModuleType const& c) const {return(name < c.name);}
00125 bool operator!=(clsModuleType c) const {return(name != c.name);}
00126 bool operator*(clsModuleType const& c) const {return(this);}
00127
00128 string getName() const {return(name);}
00129 bool addTranis(string s);
00130 bool addPort(string s);
00131 void setArea(string s){area = s;}
00132 string getArea(){return(area);}
00133 void setPower(string s){power = s;}
00134 string getPower(){return(power);}
00135 set<tMTypeData, lt_mtdata>::iterator getSTranisBegin(){return(setOfTRANIS.begin());}
00136 set<tMTypeData, lt_mtdata>::iterator getSTranisEnd(){return(setOfTRANIS.end());}
00137 set<string>::iterator getSPortsBegin(){return(setOfPorts.begin());}
00138 set<string>::iterator getSPortsEnd(){return(setOfPorts.end());}
00139 };
00140
00141 typedef map<string, clsModuleType>::value_type vt_moduletype;
00142
00143
00144
00145
00153 class clsWire
00154 {
00155 public:
00156 string from_module;
00157 string from_port;
00158 int from_bit;
00159 string to_module;
00160 string to_port;
00161 int to_bit;
00162
00163 string from_composed;
00164 string to_composed;
00165 string composed;
00166
00167 bool orig;
00168
00169
00179 clsWire(string fm, string fp, int fb, string tm, string tp, int tb, bool orig=true);
00180 ~clsWire(){};
00181
00182
00183 bool operator<(clsWire const& c) const {return(composed < c.composed);}
00184 bool operator!=(clsWire const& c) const {return(composed != c.composed);}
00185 bool operator*(clsWire const& c) const {return(this);}
00186
00187 void setOrig(bool v) { orig = v; }
00188 bool getOrig() const { return(orig); }
00189 };
00190
00191
00192
00193
00196 typedef struct ta_data
00197 {
00198 unsigned long nbitsC;
00199 unsigned long nclksC;
00200 unsigned long nbitsO;
00201 unsigned long nclksO;
00202
00203 double multCprev;
00204 double multCctrl;
00205 double multOprev;
00206 double multOctrl;
00207
00208 double con;
00209 double obs;
00210 double tst;
00211 }
00212 t_TAdata;
00213
00214
00215
00216
00223 class clsBit
00224 {
00225
00226 int bit_number;
00227 int node_type;
00228 bool orig;
00229
00230 t_TAdata ta_data;
00231
00232 public:
00233
00239 clsBit(int bn, int nt, bool orig=true);
00240 ~clsBit();
00241
00242
00243 bool operator<(clsBit const& c) const {return(bit_number < c.bit_number);}
00244 bool operator!=(clsBit c) const {return(bit_number != c.bit_number);}
00245 bool operator*(clsBit const& c) const {return(this);}
00246
00247 int getNumber() const {return(bit_number);}
00248 int getType() const {return(node_type);}
00249 t_TAdata getTAdata() const {return(ta_data);}
00250 void setTAdata(t_TAdata _ta_data) {ta_data = _ta_data;}
00251 void clrTAdata(){ta_data.nbitsC=ta_data.nclksC=ta_data.nbitsO=ta_data.nclksO=0;
00252 ta_data.multCprev=ta_data.multCctrl=ta_data.multOprev=ta_data.multOctrl=ta_data.con=ta_data.obs=ta_data.tst=0.0;}
00253 void evalTst() {ta_data.tst = ta_data.con * ta_data.obs; }
00254 void setOrig(bool v) { orig = v; }
00255 bool getOrig() const { return(orig); }
00256 };
00257
00258 typedef map<int, clsBit>::value_type vt_bit;
00259
00260
00261
00262
00271 class clsPort
00272 {
00273
00274 string name;
00275 int node_type;
00276 int lbit;
00277 int hbit;
00278 bool orig;
00279
00280 t_TAdata ta_data;
00281
00282 public:
00283 map<int, clsBit> mapBit;
00284
00291 clsPort(string nm, int nt, int w, bool orig=true);
00292
00299 clsPort(string nm, int nt, int hb, int lb, bool orig=true);
00300 ~clsPort();
00301
00302 bool operator<(clsPort const& c) const {return(name < c.name);}
00303 bool operator!=(clsPort c) const {return(name != c.name);}
00304 bool operator*(clsPort const& c) const {return(this);}
00305
00306 string getName() const {return(name);}
00307 int getType() const {return(node_type);}
00308 int getWidth() const {return(hbit-lbit+1);}
00309 int getLBit() const {return(lbit);}
00310 int getHBit() const {return(hbit);}
00311
00315 bool addBit(int bn, int nt, bool orig=true);
00316 bool addBits(bool orig=true){bool res=false; int i; for(i=lbit; i<=hbit; i++) res|=addBit(i, node_type, orig); return(res);}
00317 clsBit *findBit(int bn){map<int, clsBit>::iterator it=mapBit.find(bn); if(it==mapBit.end()) return(NULL); else return(&(*it).second);}
00318 map<int, clsBit>::iterator getMapBitBegin(){return(mapBit.begin());}
00319 map<int, clsBit>::iterator getMapBitEnd(){return(mapBit.end());}
00320 t_TAdata getTAdata() const {return(ta_data);}
00321 void setTAdata(t_TAdata _ta_data) {ta_data = _ta_data;}
00322 void clrTAdata(){ta_data.nbitsC=ta_data.nclksC=ta_data.nbitsO=ta_data.nclksO=0;
00323 ta_data.multCprev=ta_data.multCctrl=ta_data.multOprev=ta_data.multOctrl=ta_data.con=ta_data.obs=ta_data.tst=0.0;}
00324
00325 int getNCon();
00326 int getNObs();
00327 int getNTst();
00328 void evalTst();
00329
00330 void setOrig(bool v) { orig = v; }
00331 bool getOrig() const { return(orig); }
00332 };
00333
00334 typedef map<string, clsPort>::value_type vt_port;
00335 typedef map<string, int>::value_type vt_strint;
00336
00337
00338
00339
00348 class clsModule
00349 {
00350
00351 string name;
00352 string type;
00353 int area;
00354 int power;
00355 map<string, clsPort> mapPort;
00356 map<string, int> mapConsts;
00357 set<tMTypeData, lt_mtdata> setOfTRANIS;
00358 bool orig;
00359
00360 public:
00361
00362
00368 clsModule(string nm, string t, bool orig = true);
00369 ~clsModule();
00370
00371
00372 bool operator<(clsModule const& c) const {return(name < c.name);}
00373 bool operator!=(clsModule c) const {return(name != c.name);}
00374 bool operator*(clsModule const& c) const {return(this);}
00375
00376 string getName() const {return(name);}
00377 string getType() const {return(type);}
00378 void setArea(int i){area = i;}
00379 int getArea(){return(area);}
00380 void setPower(int i){power = i;}
00381 int getPower(){return(power);}
00382 bool addPort(string nm, int nt, int w, bool orig=true);
00383 bool addPort(string nm, int nt, int hbit, int lbit, bool orig=true);
00384 bool addInterface(clsModuleType *mtptr, bool orig=true);
00385 bool bitsExist(string bits);
00386 bool addTranis(string s, bool orig=true);
00387 set<tMTypeData, lt_mtdata>::iterator getSTranisBegin(){return(setOfTRANIS.begin());}
00388 set<tMTypeData, lt_mtdata>::iterator getSTranisEnd(){return(setOfTRANIS.end());}
00389 void eraseTranis(set<tMTypeData, lt_mtdata>::iterator t) {setOfTRANIS.erase(t);}
00390 bool addTranspData(clsModuleType *mtptr, bool orig=true);
00391
00392 clsPort *findPort(string nm){map<string, clsPort>::iterator it=mapPort.find(nm); if(it==mapPort.end()) return(NULL); else return(&(*it).second);}
00393 map<string, clsPort>::iterator getMapPortBegin(){return(mapPort.begin());}
00394 map<string, clsPort>::iterator getMapPortEnd(){return(mapPort.end());}
00395 void erasePort(map<string, clsPort>::iterator p) {mapPort.erase(p);}
00396 bool addConst(string s_names, string s_values);
00397 int evalExpr(string nm);
00398 int getConstVal(string nm){map<string, int>::iterator it=mapConsts.find(nm); if(it==mapConsts.end()) return(-1); else return((*it).second);}
00399 map<string, int>::iterator getMapConstsBegin(){return(mapConsts.begin());}
00400 map<string, int>::iterator getMapConstsEnd(){return(mapConsts.end());}
00401
00402 void setOrig(bool v) { orig = v; }
00403 bool getOrig() const { return(orig); }
00404
00405 bool changeTypeTo(string type);
00406 bool typeBack();
00407 };
00408
00409 typedef map<string, clsModule>::value_type vt_mod;
00410 class clsDesign;
00411
00412
00413
00414
00425 class clsCircuit
00426 {
00427
00428 string name;
00429 map<string, clsPort> mapPort;
00430 map<string, clsModule> mapMod;
00431 set<clsWire> setOfWires;
00432
00433 int area;
00434 int power;
00435
00436 public:
00437 double con;
00438 double obs;
00439 double tst;
00440
00441 double rcon;
00442 double robs;
00443 double rtst;
00444
00445
00446 clsCircuit(string nm);
00447 ~clsCircuit();
00448
00449
00450 bool operator<(clsCircuit const& c) const {return(name < c.name);}
00451 bool operator!=(clsCircuit c) const {return(name != c.name);}
00452 bool operator*(clsCircuit const& c) const {return(this);}
00453
00454 string getName() const {return(name);}
00455 int getNAllBits();
00456 int getNBits();
00457 int getNClks();
00458 bool addPort(string nm, int nt, int w, bool orig=true);
00459 clsPort *findPort(string nm){map<string, clsPort>::iterator it=mapPort.find(nm); if(it==mapPort.end()) return(NULL); else return(&(*it).second);}
00460 map<string, clsPort>::iterator getMapPortBegin(){return(mapPort.begin());}
00461 map<string, clsPort>::iterator getMapPortEnd(){return(mapPort.end());}
00462 int getNallPorts();
00463 double getAvgPortWidth();
00464 bool addMod(string nm, string t, bool orig=true);
00465 clsModule *findMod(string nm){map<string, clsModule>::iterator it=mapMod.find(nm); if(it==mapMod.end()) return(NULL); else return(&(*it).second);}
00466 map<string, clsModule>::iterator getMapModBegin(){return(mapMod.begin());}
00467 map<string, clsModule>::iterator getMapModEnd(){return(mapMod.end());}
00468 int getNmodules() const {return(mapMod.size());}
00469 bool addWire(clsWire w);
00470 bool connectPorts(string sm, string sp, string dm, string dp, bool reverse, bool orig=true);
00471 set<clsWire>::iterator getSetOfWiresBegin(){return(setOfWires.begin());}
00472 set<clsWire>::iterator getSetOfWiresEnd(){return(setOfWires.end());}
00473 void eraseWire(set<clsWire>::iterator w) {setOfWires.erase(w);}
00474 int getNwires() const {return(setOfWires.size());}
00475
00476 void evalArea(){area=0; map<string, clsModule>::iterator it=mapMod.begin(); for(;it!=mapMod.end();it++){ area += (*it).second.getArea(); } }
00477 int getArea(){ evalArea(); return(area); }
00478 void evalPower(){power=0; map<string, clsModule>::iterator it=mapMod.begin(); for(;it!=mapMod.end();it++){ power += (*it).second.getPower(); } }
00479 int getPower(){ evalPower(); return(power); }
00480
00481
00482 int controlability_analysis(set<string> *marked_bits);
00483 int observability_analysis(set<string> *marked_bits);
00484 int testability_analysis();
00485 void evalTst();
00486
00487
00488 set<string> get_untestableBits(tmodeSel mode);
00489 set<string> get_badTsourceBits(int type);
00490 set<string> get_regNames(string fname);
00491 set<string> get_scanRegCandidateBits(set<string> regs);
00492 set<string> get_scanRegCandidates(set<string> regs);
00493
00494
00495 void export_TAresults_txt(string fname);
00496 void export_TAresults_htm(string fname);
00497 void export_TAresults_tex(string fname);
00498
00499
00500 set<string> get_scan_notation(string fname);
00501 bool implement_scan_notation(string fsname, string frname);
00502 bool deimplement_changes();
00503
00504 void implementDft();
00505 };
00506
00507 typedef map<string, clsCircuit>::value_type vt_cir;
00508
00509
00510
00511
00521 class clsDesign
00522 {
00523
00524 string name;
00525 map<string, clsCircuit> mapCir;
00526 map<string, clsModuleType> mapModType;
00527
00528 int area;
00529 int power;
00530
00531 public:
00532
00533 clsDesign(string nm);
00534 ~clsDesign();
00535
00536
00537 string getName() const {return(name);}
00538 bool addCir(string nm);
00539 clsCircuit *findCir(string nm){map<string, clsCircuit>::iterator it=mapCir.find(nm); if(it==mapCir.end()) return(NULL); else return(&(*it).second);}
00540 map<string, clsCircuit>::iterator getMapCirBegin(){return(mapCir.begin());}
00541 map<string, clsCircuit>::iterator getMapCirEnd(){return(mapCir.end());}
00542 bool addModType(string nm);
00543 clsModuleType *findModType(string nm);
00544 void syncModWithType(clsModule *mptr);
00545 void dump_info();
00546
00547 void evalArea(){area=0; map<string, clsCircuit>::iterator it=mapCir.begin(); for(;it!=mapCir.end();it++){ area += (*it).second.getArea(); } }
00548 int getArea(){ evalArea(); return(area); }
00549 void evalPower(){power=0; map<string, clsCircuit>::iterator it=mapCir.begin(); for(;it!=mapCir.end();it++){ power += (*it).second.getPower(); } }
00550 int getPower(){ evalPower(); return(power); }
00551
00552
00553 void export_TAresults_txt(string fname);
00554
00555
00556 void implementDft(string cir="");
00557 void deimplement_changes(string cir="");
00558 };
00559
00560 #endif