HAVEN

HAVEN is a SystemVerilog verification framework that allows users to run either a non-accelerated or an accelerated version of the same testbench with a cycle-accurate time behaviour. The non-accelerated version runs entirely in a simulator, while the accelerated version uses an FPGA to accelerate verification runs. Providing two versions allows to use the framework efficiently in different stages of the design flow, from debugging base system functions in a simulator to stress testing with millions of test vectors using hardware acceleration. After creating the basic verification environment, switching between the two versions is as easy as changing a single parameter of the verification.

The components of the verification environment differ according to the selected version of the framework as illustrated in following figure. The sections HAVEN: Non-accelerated version and HAVEN: Accelerated version contain their detailed description.