In the current industry environment, the multiprocessor Multiprocessor System on the Chip (MPSoC) technology is often used for embedded systems production. The technology enables integration of several application specific instruction-set processors (ASIPs) and memories into one chip. It is important to reduce the design and exploration time of the architecture. This can be reached by shifting tasks into programmable parts. The programmable parts can be described by Higher Level Languages. The use of the HLL for description significantly shortens the time of the system design. We introduce a project which deals with a problematic of MPSoC design, programming, simulation and realization.

The Lissom project runs at Brno University of Technology, Faculty of Information Technology, Czech Republic. The project is focused on two basic scopes. The first scope is a development of an architecture description language for the MPSoC description. The second scope is a transformation of MPSoC description into advanced software tools (e.g. C compiler, simulator, etc.) or hardware realization of each processor.

Look at the presentation of our research group from the event of Pojdte delat vedu na FIT (28.3.2007) - in Czech language.


This research is supported by the grant of MPO Czech Republic, FT-TA3/128-- Language and development environment for microprocessor design, FR-TI1/038-- System for programming and realization of embedded systems, the Research Plan No. MSM, 0021630528 -- Security-Oriented Research in Information Technology and by Smart Multicore Embedded SYstems.



It is now possible to new register on our site. As the main feature, the maximal allowed decompilation time is doubled for all registered users.


A new version (1.5) of the retargetable decompiler is now up and running!


Mission possible: obtain a source code from a real-world malware. A case study using our retargetable decompiler. Read more.


We have created a new version (1.4) of the retargetable decompiler. The main features of this version are a basic support of decompiling binaries created in Delphi, unpacking of files packed with several widely used packers and protectors, and various improvements of the readability of the decompiled code.


A new release (1.3) of the retargetable decompiler has just been made. Among the main features of this release belong basic support of Windows API, new optimizations, more configuration options in the online decompilation form, and a newsletter.


Today, we have made a new version (1.2) of the retargetable decompiler. The main features of this version are a base implementation of FPU (Floating-Point Unit) on Intel x86, decoding speedup, elimination of unreachable code, and renaming of variables.


We have made a new version (1.1) of the retargetable decompiler. As of this version, the decompiler supports decompilation of binary files in the MS Windows PE format for the Intel x86 architecture.


We are pleased to introduce a new online decompilation service .


The decompiler now supports decompilation of Linux ELF binary files for the Intel x86 architecture.


The official website of the retargetable decompiler has been launched.


ASIC synthesis of Codasip Startup Processor Platform Codix v1 - Technology ALP 0.18um (EM Microelectronic), Constrains 50 MHz, memory delay est. 10 ns (1/2 period): Area=316299 um2, Power=2.516 mW. We are focusing on power reduction now.


We release version 1.0.6 of the Codasip Studio. It is bugfixing release. We release version 1.5.0 of the Codasip Framework. It fixes some major bugs and brings several new features.


The retargetable decompiler now supports ARMv7+Thumb architecture. Intel x86 coming soon.


Codix, is new 32-bit high performance, low area customizable synthesizable processor core. The Codix processor core enables the execution of Microsoft .NET Micro Framework or various other software applications, such as audio-video codecs etc.


Codea2 is small 16-bit low power, cache-less digital signal soft-processor. The processor utilizes Harvard architecture with separated address spaces for data and the program.


Retargetable decompiler has been successfully tested on the MIPS32 architecture. Next target is the ARMv7 architecture.


ASIC realization of 16-bit processor ADOP with 5 stages pipeline with a control logic for the hazard detection in technology AMIS CMOS 0.35 um.


Start-up of Codasip portal.


Lissom will be participating in the UNIVERSITY BOOTH of the Design, Automation & Test Conference DATE 2011 in Grenoble, France on March 14-18, 2011.


2nd version of the ISAC manual is available.


RTL simulator is available.


ISAC model of MSP 430 has been created. Simulation and programming tools for FITkit platform are available.


Support of VLIW instruction encoding and compression has been added.


Generator of function units in VHDL is available.


Cycle-accurate dynamic compiled simulator is available, so simulation of self-modifying code is possible.


Language sensitive editor for ISAC language is available.


Added support for static compiled simulator. The static compiled simulator of Chili3 VLIW multimedia microprocessor is almost ten times faster then the interpreted simulator. Furthermore, work on dynamic compiled simulator is in progress.


We lost our collegue in tragic accident. You were a great researcher, collegue and friend Roman. We will miss you.


Research at the field of decompiler of C language started.


Created synchronous and asynchronous version of distributed MPSoC simulation.


Improved concept of single processor's profiler.


Speed of the MIPS32's simulator generated from the ISAC language is about 3 MHz better than the speed of the generated simulator from the ArchC language. Average MIPS32 ISAC simulator's speed is 30 MHz.


Third version of the instruction decoders' and controllers' generator in VHDL from ISAC model is available. For the generated hardware description is used a structural level of the VHDL and the generator's output is always synthesizable (area's utilization of FPGA Virtex 4 after synthesis is 95% for complex ISAC model).


Czech lecture about ASIP simulation and LISA architecture description language.


ISAC model of MIPS microprocessor. Speed of our generated simulator is 9 MHz, speed of the common handwritten one is about 3 Mhz.


ISAC model of Chili3 multimedia microprocessor from OnDemand Microelectronic Austria. Speed of our generated simulator is 1,6 MHz, speed of the common handwritten one is 0,7 MHz.


Lissom group's czech presentation at the event of Poj�te d�lat v�du na FIT.


New release of Eclipse plugin and tools are available.


Translator from the ASIP model in the ISAC language to the synthesizable central controller and instruction decoders in the VHDL language is available.


Group's presentation at Poj�te d�lat v�du na FIT. The presentation in power point or pdf format.


Second generation of software tools is available now. Tools are available using Eclissom eclipse plugin.


Prototype of the tool for the implementation of the microprocessor in VHDL based on the model in ISAC


Cycle accurate simulation supported (including simulation of pipeline)


Lissom WebIDE 2.0 launched


Eclissom - plugin for Eclipse available


Support of basic ACTIVATION section of operations in software tools


Support of CODINGROOT sections in tools - modeling of VLIW possible


New website launched